Low power domino logic circuits in deep-submicron technology using CMOS

Garg, Sandeep; Gupta, Tarun Kumar

doi:10.1016/j.jestch.2018.06.013

Cited by 32 publications

(18 citation statements)

References 20 publications

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“…This amplitude of noise pulse obtained at the output is equal to the UNG of the circuit. UNG is given by 30,[32][33][34][35][36] : Figure 17 and 18 shows that proposed (DCHSDL) technique has greater UNG for 2, 4, 8 and 16 input OR gates in comparison with existing domino techniques in CMOS and CNFET technologies. Proposed technique shows an improvement of 1.05× to 1.63× in UNG in comparison with various existing techniques.…”

Section: Resultsmentioning

confidence: 98%

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Garg

Gupta

Pandey³

2019

Circuit Theory & Apps

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CNFET devices are preferred over CMOS devices for designing high-speed digital circuits. This paper introduces a new technique Dual Chirality High-speed Domino Logic (DCHSDL) for implementing low power and high-speed domino circuits in CNFET technology. Simulations are carried out for 32 nm Stanford CNFET model in HSPICE for 2, 4, 8 and 16 input domino OR gates at a clock frequency of 200 MHz on a DC supply voltage of 0.9 V. The proposed domino technique shows maximum power reduction of 82.55% and maximum delay reduction of 57.97% compared to CPVT technique in CNFET technology at a frequency of 200 MHz. The proposed circuit shows maximum power reduction of 97.90% compared to its analogous circuit in CMOS technology for a 2-input domino OR gate. The proposed technique shows maximum improvement of 1.05× to 1.63× in unity noise gain (UNG) compared to various existing techniques in CNFET technology at a frequency of 200 MHz. The 1-bit Full Adderdesigned using the proposed technique shows a power reduction of 16.91% and a delay reduction of 23.64% compared to standard FDL 1-bit Full Adder. K E Y W O R D SCNFET, Domino, Dynamic, FOM, VLSI

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Section: Resultsmentioning

confidence: 98%

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Garg

Gupta

Pandey³

2019

Circuit Theory & Apps

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“…According to Zhou et al [7] for CMOS circuit multi-threshold CMOS technology is an effective method to reduce subthreshold leakage power which satis es design of low power and high performance requirements. Garg et al [8] proposes Foot Driven Stack Transistor Domino Logic (FDSTDL) for designing CMOS domino logic gates which reduces leakage power with better noise performance. Asyaei [9] presented a new leakage tolerant domino circuit that provides higher noise immunity with lower power consumption and without signi cant delay increment for wide fan-in gates.…”

Section: Literature Reviewmentioning

confidence: 99%

Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

Magraiya¹,

Gupta²,

Garg³

2021

Preprint

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The leakage current is prime concern in the modern portable battery operated device. However, various techniques are presented and performance is evaluated using MOSFET and FinFET devices. To further reduce leakage current for improved battery backup in portable devices, new devicesnamely Carbon Nano Tube Field Effect transistors (CNTFETs) can be used for design of different digital circuits. In this paper, subthreshold leakage power of dual chiral CNTFET based domino circuit is investigated and also the results are compared with single chiral CNTFET domino circuits. For better performance, threshold voltage of CNTFET in critical path is varied by changing the diameter or chirality of carbon nanotube. Subthreshold leakage power saving in dual chiral standard and LECTOR based domino circuits for OR2, OR4, OR8 & OR16 for low temperature (25°C) & low input ranges from 90.36- 95.96% and from 91.97-97.3%; for low temperature & high input ranges from 90.66-95.23% and from 92.85-96.39%; for high temperature (110°C) & low input ranges from 89.24- 99.73% and from 27.5-99.83%; for high temperature & high input ranges from 89.65-97.86% and from 91.85-99.76% when compared with single chiral standard and LECTOR based domino circuits respectively.

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“…Various parameters varied for MOS transistors during Monte Carlo simulation are threshold voltage, mobility, oxide thickness, The proposed design is suitable for low power applications with low power dissipation, low area and a little loss in performance. In order to perform the noise analysis, Unity Noise Gain (UNG) [15] is calculated. UNG is the amount of DC noise at all inputs that result in the same amount of noise at the output node [16].…”

Section: Monte Carlo Simulation and Noise Analysismentioning

confidence: 99%

A Novel Domino Logic with Modified Keeper in 16nm CMOS Technology

Mehra¹,

Singhal²,

TRIPATHI³

2019

ELS

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Domino logic is a clocked CMOS (Complementary Metal-Oxide Semiconductor) logic with fewer transistors than static CMOS logic. A PMOS (P-type Metal-Oxide Semiconductor) transistor, known as “keeper”, is included in the design to improve the noise tolerance performance and to reduce the leakage current. The aspect ratio i.e. W/L of the keeper (W=width and L=length) is kept low for the correct functionality of the domino logic. This paper proposes a domino logic with modified keeper in order to improve the circuit with respect to power and area as compared to various existing techniques of domino logic i.e. clock delayed domino logic (CDD), high speed domino logic (HSD), multi threshold high speed domino logic (MHSD), clock delayed sleep mode domino logic (CDSMD), sleep switch domino logic (SSDD), PMOS only sleep switch domino logic (PSSDD), reduced delay variations domino logic (RDVD) and Foot Driven Stack Transistor Domino Logic (FDSTDL). The proposed as well as existing domino logics, for 8-input as well as 16-input OR gate in 16nm CMOS technology, are simulated for different values of W/L of keeper with W/L ratio ranging from 1 to 6. The power-delay-product(PDP) of proposed design has improved as compared to the existing designs. For 8-input OR gate and W/L=6, PDP had improved to maximum of 99.99% for CDD and minimum of 38.09% for SSDD.

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Low power domino logic circuits in deep-submicron technology using CMOS

Cited by 32 publications

References 20 publications

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

A 1‐bit full adder using CNFET based dual chirality high speed domino logic

Design of CNTFET Based Domino Wide OR Gates Using Dual Chirality for Reducing Subthreshold Leakage Current

A Novel Domino Logic with Modified Keeper in 16nm CMOS Technology

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