Domino logic is a clocked CMOS (Complementary Metal-Oxide Semiconductor) logic with fewer transistors than static CMOS logic. A PMOS (P-type Metal-Oxide Semiconductor) transistor, known as “keeper”, is included in the design to improve the noise tolerance performance and to reduce the leakage current. The aspect ratio i.e. W/L of the keeper (W=width and L=length) is kept low for the correct functionality of the domino logic. This paper proposes a domino logic with modified keeper in order to improve the circuit with respect to power and area as compared to various existing techniques of domino logic i.e. clock delayed domino logic (CDD), high speed domino logic (HSD), multi threshold high speed domino logic (MHSD), clock delayed sleep mode domino logic (CDSMD), sleep switch domino logic (SSDD), PMOS only sleep switch domino logic (PSSDD), reduced delay variations domino logic (RDVD) and Foot Driven Stack Transistor Domino Logic (FDSTDL). The proposed as well as existing domino logics, for 8-input as well as 16-input OR gate in 16nm CMOS technology, are simulated for different values of W/L of keeper with W/L ratio ranging from 1 to 6. The power-delay-product(PDP) of proposed design has improved as compared to the existing designs. For 8-input OR gate and W/L=6, PDP had improved to maximum of 99.99% for CDD and minimum of 38.09% for SSDD.
In this paper, the design and simulation of cylindrical, co-axial, Carbon Nanotube Field Effect Transistor (CNTFET) is presented using online Fettoy tool of Nanohub. This tool can provide various characteristics of CNTFET, like transfer characteristics, output characteristics, average velocity vs. gate voltage etc. To simulate the CNTFET we have considered the value of diameter of carbon nanotube 1nm which is of (13,0) chirality. Gate insulator thickness is taken as 1.5nm and the dielectic constant of the material used as gate oxide is k=20 , which is the value shown by ZrO 2 .A comparison between designed CNTFET and conventional MOSFET shows improvement of various parameters which plays a significant role in design of logic circuits. With these improved properties of CNTFETs it can be concluded that it is very useful in designing of reversible logic circuits. Also, it is very efficient in terms of power consumption, speed of operations, and leakage current over conventional MOSFETs.
The presented paper deals with the effect of UV radiation and change in rate of recombination on the operation of metal oxide gas sensors. The performance of a simple metal oxide sensor is simulated first and the relation between absorbed gas concentration and resistance is monitored in absence of UV radiation. Later, the same performance is monitored in the presence of UV radiation on the sensor with the occurrence of surface recombination phenomenon. The performances are simulated on MATLAB. The Grain boundary resistance (R gb ), neck resistance (R n ) and total resistance (R) were obtained by simulating standard equation on MATLAB software. The effect of the surface recombination on absorption of gas concentration and change in resistance is also taken into account. It has been observed that the resistance of the sensors depends on the grain size (L), flux density, absorbed gas concentration (N r ), depletion width (W).
This study presents different topologies for the assignment of dual threshold voltage and dual gate oxide thickness in 16 nm complementary metal-oxide-semiconductor technology. The objective is to optimise the circuit in terms of static power dissipation, delay, and power-delay-product (pdp). Topologies namely direct, grouping, and divide-by-2 are simulated for (A + B) ⋅ C and conventional 1-bit full adder circuits. Results of the proposed topologies are compared with some of the existing techniques of leakage reduction i.e. dual-V th , dual-T ox and supply switching with ground collapse (SSGC). 1-bit full adder circuit using direct topology reduces static power to 99.98, 96.71, and 95.86% as compared to static power in dual-V th , dual-T ox , and SSGC techniques, respectively. The pdp of the circuit is significantly improved using proposed topologies. Thus, these topologies can be used for low power and high-performance applications with no area overhead.
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