Abstract:This study presents different topologies for the assignment of dual threshold voltage and dual gate oxide thickness in 16 nm complementary metal-oxide-semiconductor technology. The objective is to optimise the circuit in terms of static power dissipation, delay, and power-delay-product (pdp). Topologies namely direct, grouping, and divide-by-2 are simulated for (A + B) ⋅ C and conventional 1-bit full adder circuits. Results of the proposed topologies are compared with some of the existing techniques of leakage… Show more
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