A Novel Domino Logic with Modified Keeper in 16nm CMOS Technology

Abstract

Domino logic is a clocked CMOS (Complementary Metal-Oxide Semiconductor) logic with fewer transistors than static CMOS logic. A PMOS (P-type Metal-Oxide Semiconductor) transistor, known as “keeper”, is included in the design to improve the noise tolerance performance and to reduce the leakage current. The aspect ratio i.e. W/L of the keeper (W=width and L=length) is kept low for the correct functionality of the domino logic. This paper proposes a domino logic with modified keeper in order to improve the circuit with respect to power and area as compared to various existing techniques of domino logic i.e. clock delayed domino logic (CDD), high speed domino logic (HSD), multi threshold high speed domino logic (MHSD), clock delayed sleep mode domino logic (CDSMD), sleep switch domino logic (SSDD), PMOS only sleep switch domino logic (PSSDD), reduced delay variations domino logic (RDVD) and Foot Driven Stack Transistor Domino Logic (FDSTDL). The proposed as well as existing domino logics, for 8-input as well as 16-input OR gate in 16nm CMOS technology, are simulated for different values of W/L of keeper with W/L ratio ranging from 1 to 6. The power-delay-product(PDP) of proposed design has improved as compared to the existing designs. For 8-input OR gate and W/L=6, PDP had improved to maximum of 99.99% for CDD and minimum of 38.09% for SSDD.

Proposed time‐mode wide fan‐in NAND and NOR gates

“…Since both the precharging time and the average power consumption are dependent on the input pattern, half of the input bits is assumed to be at logic “1” and the other half is assumed to be at logic “0.” Although both the power consumption and the PDP of the scheme of Angeline and Bhaaskaran 47 are smaller than those of the proposed scheme, it must be noted that the load capacitance of this scheme is just the parasitic capacitance at the gate terminal of the keeper. Other schemes for comparison can be found in other studies 48–55 …”

A Charge-Accumulation Based High-Performance CMOS Circuit

“…In [52], the keeper was controlled using a controlling network; 31.42% and 31.91% reductions in the power consumption and power-delay product, respectively, were reported for 32-inputs OR gate. In [53], the contention current was eliminated at the beginning of the evaluation phase by modifying the keeper; specifically, an NMOS device was added in series to the keeper. In [54], a multiplexer was used for gating the clock signal, thus reducing the power consumption.…”