A Charge-Accumulation Based High-Performance CMOS Circuit

Abstract

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from degraded performance. In this paper, a circuit that depends on charge accumulation is proposed as an alternative to conventional CMOS design. The proposed scheme is investigated quantitatively and verified by simulation using predictive technology model (PTM) of the 45 nm CMOS technology with a power-supply voltage, VDD, equal to 1 V. Although the proposed scheme suffers from more sensitivity to process variations compared to static CMOS, the comparative analysis and simulation results confirm the superiority of the proposed scheme from the points of view of speed, area, power consumption, and unity-noise gain. It is verified that the proposed scheme has a smaller area, power consumption, and delay compared to the conventional CMOS design when the number of inputs, n, exceeds four, two, and three, respectively. The impacts of process variations, component mismatches, and technology scaling are also investigated. The speed advantage gained from the proposed scheme is expected to be more obvious when operating in the subthreshold region. A figure of merit including the unity-noise gain, area, power consumption, and time delay is defined and the proposed scheme showed superior performance compared to the conventional CMOS logic when n exceeds four. Finally, the proposed scheme was compared with various previous schemes.

Proposed time‐mode wide fan‐in NAND and NOR gates

“…Specifically, with wide fan‐in dynamic OR gates realized using the conventional dynamic logic, the leakage current through the PDN becomes relatively large, thus requiring the use of a large keeper. This results in an increased contention current with the associated degradation in speed 58 . This limitation is not found in the proposed time‐mode scheme as there are no keepers with their associated contention currents.…”

“…This results in an increased contention current with the associated degradation in speed. 58 This limitation is not found in the proposed time-mode scheme as there are no keepers with their associated contention currents.…”

“…The main limitation of the conventional dynamic logic is the reduced noise immunity with increasing the fan-in. 58 Specifically, with wide fan-in dynamic OR gates realized using the conventional dynamic logic, the leakage current through the PDN becomes relatively large, thus requiring the use of a large keeper. This results in an increased contention current with the associated degradation in speed.…”