Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique

Namin, Shoaleh Hashemi; Wu, Huapeng; Ahmadi, M.

doi:10.1109/tvlsi.2016.2585980

Cited by 13 publications

(2 citation statements)

References 33 publications

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“…If we increase the digit size, the number of cycles decreases more effectively and the improvement of time increases. The area is less than other implementations and slightly more than [28]. The proposed structure has the lowest area × time compared with other structures.…”

Section: Comparison Of the Performance Of The Multipliersmentioning

confidence: 89%

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Efficient implementation of digit‐serial Montgomery modular multiplier architecture

Fatemi

Zare

Khavari

et al. 2019

IET Circuits, Devices & Systems

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The importance of security in communications has made cryptography one of the most important research for designers. Montgomery modular multiplication is one of the best methods used in cryptosystems. These multipliers can be implemented in different ways including digit-serial architecture. The digit-serial multiplier is an efficient structure for low power and high-speed applications. The architecture of digit-serial multiplier can benefit from the advantage of both serial and parallel structures. This study presents a new digit-serial Montgomery modular multiplier architecture, which takes up less area by reducing internal blocks of the structure. The latency and design complexity of the proposed digit-serial Montgomery multiplier is less than many other similar designs. The critical path delay of the proposed architecture is reduced compared to similar works. The proposed circuit has the flexibility to be used in a large number of bits and can be used for any size of the digit. The simulation results of the proposed multiplier are presented. 2 Preliminaries Suppose an m bit integer number is expressed as a m − 1 ⋯a 1 a 0 that the coefficient a i can be 0 or 1. Based on (1), the ordinary modular multiplication of two integer numbers A and B is performed by dividing A × B into modulus N which N is an odd number

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Section: Comparison Of the Performance Of The Multipliersmentioning

confidence: 89%

“…Furthermore, it is flexible for any number of digits and digit sizes without any change in the structure of multiplier. Some structures have a problem with the number of digits or have separate structures for odd and even digit size [28], which means some extra circuits are needed for detection of odd or even digit size.…”

Section: Introductionmentioning

confidence: 99%

Efficient implementation of digit‐serial Montgomery modular multiplier architecture

Fatemi

Zare

Khavari

et al. 2019

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

A survey paper on design and implementation of multipliers for digital system applications

Immareddy

Arunmetha

2022

Artif Intell Rev

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Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication

Rashidi

2020

J Hardw Syst Secur

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Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique

Cited by 13 publications

References 33 publications

Efficient implementation of digit‐serial Montgomery modular multiplier architecture

Efficient implementation of digit‐serial Montgomery modular multiplier architecture

A survey paper on design and implementation of multipliers for digital system applications

Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication

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