A survey paper on design and implementation of multipliers for digital system applications

Immareddy, Srikanth; Arunmetha, S.

doi:10.1007/s10462-021-10113-0

Cited by 14 publications

(4 citation statements)

References 102 publications

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“…But this assumption is not true for DSP-built designs that have vendor-provided optimized circuit design. The approximate computing architecture of the DSP (Digital Signal Processor) units using efficient algorithms can perform multiplication efficiently with less power and with high speed (Immareddy and Sundaramoorthy, 2022 ). DSP IP slices are provided in almost all 7-series boards such as Xilinx Artix-7, Kintex-7, Virtex-7 and Zynq-7000.…”

Section: Reconfigurable Esn Architecture Designmentioning

confidence: 99%

Leveraging neuro-inspired AI accelerator for high-speed computing in 6G networks

Lin,

Azmine,

Liang

et al. 2024

Front. Comput. Neurosci.

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The field of wireless communication is currently being pushed to new boundaries with the emergence of 6G technology. This advanced technology requires substantially increased data rates and processing speeds while simultaneously requiring energy-efficient solutions for real-world practicality. In this work, we apply a neuroscience-inspired machine learning model called echo state network (ESN) to the critical task of symbol detection in massive MIMO-OFDM systems, a key technology for 6G networks. Our work encompasses the design of a hardware-accelerated reservoir neuron architecture to speed up the ESN-based symbol detector. The design is then validated through a proof of concept on the Xilinx Virtex-7 FPGA board in real-world scenarios. The experiment results show the great performance and scalability of our symbol detector design across a range of MIMO configurations, compared with traditional MIMO symbol detection methods like linear minimum mean square error. Our findings also confirm the performance and feasibility of our entire system, reflected in low bit error rates, low resource utilization, and high throughput.

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Section: Reconfigurable Esn Architecture Designmentioning

confidence: 99%

Leveraging neuro-inspired AI accelerator for high-speed computing in 6G networks

Lin,

Azmine,

Liang

et al. 2024

Front. Comput. Neurosci.

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“…Most important DSP (Digital Signal Processing) algorithms, such as digital finite and infinite impulse response filters, DFT, FFT, convolution, and other methods, use multiply-accumulate computations (8) . For any DSP method, the number of multiplications is the primary factor that defines the entire processing time because the multiplication time is typically considerably longer than the addition time; hence, multiplier design and implementation are more concentrated in DSP techniques (9) .…”

Section: Motivationmentioning

confidence: 99%

“…Vedic mathematics is the foundation of the Vedic multiplier (8) . The 16 sutras of Urdhva Tiryagbhyam provide the foundation of Vedic mathematics.…”

Section: Motivationmentioning

confidence: 99%

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Prasad,

Babu,

Kasiselvanathan

et al. 2024

IJST

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Objectives: This work objective is to construct an FPGA-based 16x16 Vedic multiplier and assess the performance of the multiplier using three distinct architectures: pipeline, wave pipeline, and modified wave pipeline in terms of delay and clock skew. Methods: The 16 × 16 Vedic multiplier was constructed and designed through four numbers of an 8x8 Vedic multiplier. For the 16x16 Vedic multiplier, the 3-stage pipeline and wave pipeline techniques are applied, and the delay performances of the Vedic multiplier are compared. Delay optimization: In the wave pipeline Vedic multiplier architecture, the delay is decreased by inserting the known delay on the longest path delay between the multiplier and adder. Clock skew optimization: The clock skew issue of the wave pipeline Vedic multiplier architecture is minimized by adjusting the setup time violation of the clock signal that is connected to the input and output registers. Findings: The delay performance of the Vedic multiplier was evaluated by the synthesis tools Xilinx 12.1, Xilinx ISE 14.2, and Altera, and based on the synthesis report, the Xilinx synthesis tool offers 73.71% delay performance for the pipeline approach and 53.39% for the wave pipeline approach compared to the Altera tool. Further delay is reduced by the proposed modified wave pipeline approach, which saves 2.122 ns of delay compared to the wave pipeline architecture. The clock skew performance was analyzed using the Time Quest timing analyzer tool, and it was minimized to 0.035 from 0.048 compared to the wave pipeline approach. Novelty: In this work, the modified wave pipeline approach has been applied to the existing Vedic multiplier architecture, and it offers less delay as well as less clock skew compared to the existing method. Hence, the performance of the Vedic multiplier with a modified wave pipelined approach was evaluated through a 3-tap FIR filter by applying a vibroarthrography signal. Keywords: Pipeline, Wave Pipeline, Vedic Multiplier, Clock skew, Set up violation, Altera quartex- II Time quest timing analyzer tool

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“…Due to its versatility, ability to fulfill specific needs and schedules, and ability to create skills beyond studies, BL has risen in demand [43][44][45][46][47][48] . Learners develop natural talents, collaborative behavior, and knowledge of technology, which are fundamental in today's networked educational environment [49][50][51][52][53][54] .…”

Section: Introductionmentioning

confidence: 99%

Design and evaluation of multimodal learning resources in blended teaching of college English

Zhang,

2024

ESP

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Higher Education (HE) is transforming towards embracing global pedagogical standards, particularly emphasizing student-centered learning models. In conjunction with these progressive initiatives, the incorporation of the Internet is aimed at enhancing course flexibility for both university instructors and students. Blended Learning (BL), a synthesis of online and face-to-face instruction, emerges as a methodology capable of leveraging the advantages inherent in both traditional classroom learning and online learning environments. The research being examined discovers the HE sector's application of globally recognized educational ethics and student-focused teaching. Online access has better-quality course flexibility. This type of education, which participates in classroom teaching with Online Education (OE), is being verified for communication skills. The research uses Moodle and a predictable informative setting to deal with several modes of education. The 49 HE pupils shared in a pre and post-test. Combining teaching improves communication skills, increasing the relationship between students and educators for a more practical education practice.

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A survey paper on design and implementation of multipliers for digital system applications

Cited by 14 publications

References 102 publications

Leveraging neuro-inspired AI accelerator for high-speed computing in 6G networks

Leveraging neuro-inspired AI accelerator for high-speed computing in 6G networks

Pipelined and Wave Pipelined Approach Based Comparative Analysis for 16x16 Vedic Multiplier

Design and evaluation of multimodal learning resources in blended teaching of college English

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