Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication

Rashidi, Bahram

doi:10.1007/s41635-019-00087-5

Cited by 9 publications

(1 citation statement)

References 40 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The possibility to configure the size of the digit allows to trade the performance with the resource utilization. Reference [22] presents a lowarea and scalable digit-serial architecture to perform polynomial basis multiplications over Z 2 [x]. Two digit-serial architectures for multiplication over Galois fields employing the normal basis representation are presented in [23], [24].…”

Section: ) Hardware Acceleratorsmentioning

confidence: 99%

Flexible and Scalable FPGA-Oriented Design of Multipliers for Large Binary Polynomials

2020

View full text Add to dashboard Cite

With the recent advances in quantum computing, code-based cryptography is foreseen to be one of the few mathematical solutions to design quantum resistant public-key cryptosystems. The binary polynomial multiplication dominates the computational time of the primitives in such cryptosystems, thus the design of efficient multipliers is crucial to optimize the performance of post-quantum public-key cryptographic solutions. This manuscript presents a flexible template architecture for the hardware implementation of large binary polynomial multipliers. The architecture combines the iterative application of the Karatsuba algorithm, to minimize the number of required partial products, with the Comba algorithm, used to optimize the schedule of their computations. In particular, the proposed multiplier architecture supports operands in the order of dozens of thousands of bits, and it offers a wide range of performance-resources trade-offs that is made independent from the size of the input operands. To demonstrate the effectiveness of our solution, we employed the nine configurations of the LEDAcrypt public-key cryptosystem as representative use cases for large-degree binary polynomial multiplications. For each configuration we showed that our template architecture can deliver a performance-optimized multiplier implementation for each FPGA of the Xilinx Artix-7 mid-range family. The experimental validation performed by implementing our multiplier for all the LEDAcrypt configurations on the Artix-7 12 and 200 FPGAs, i.e., the smallest and the largest devices of the Artix-7 family, demonstrated an average performance gain of 3.6x and 33.3x with respect to an optimized software implementation employing the gf2x C library.

show abstract

Section: ) Hardware Acceleratorsmentioning

confidence: 99%