Security of currently deployed public-key cryptography algorithms is foreseen to be vulnerable against quantum computer attacks. Hence, a community effort exists to develop post-quantum cryptography (PQC) algorithms, most notably the NIST PQC standardization competition. In this work, we have investigated how lattice-based candidate algorithms fare when implemented in hardware. To achieve this, we have assessed 12 lattice-based algorithms in order to identify their basic building blocks. We assume the algorithms will be implemented in an application-specific integrated circuit (ASIC) platform and the targeted technology is 65 nm. To estimate the characteristics of each algorithm, we have assessed the following characteristics: memory requirements, use of multipliers, and use of hashing functions. Furthermore, for these building blocks, we have collected area and power figures for all studied algorithms by making use of commercial memory compilers and standard cells. Our results reveal interesting insights about the relative importance of each building block for the overall cryptosystem, which can be used for guiding ASIC designers when selecting an algorithm or when deciding where to focus optimization efforts such that the final design respects requirements and design constraints.
The security and dependability of embedded systems are increasing due to the sensitive and condensed structure of nanodevices. As the chip area shrinks and the technologies upgrade, the probability of Single Event Upset or Multi Bit Upset proliferate which may lead to unexpected results. This article presents a fault-injection tool called EFIC-ME (Emulation based Fault Injection Control and Monitoring Enhancement) using an emulation technique with a reasonable contribution to flexibility and controllability. Existing emulation based fault-injection tools, targeting Field Programmable Gate Arrays (FPGA), reveal high efficiency and low emulation time, but they still lack the control of fault injection time. The proposed tool (EFIC-ME) achieves a low emulation time and provides a sophisticated way to inject the fault in a specific location at a specific clock cycle inside the Design Under Test (DUT). Additionally, it also employs an observability mechanism to monitor the current state of flip-flops on a user defined time. In the context of high emulation speed, it provides an Opal Kelly FPGA interface between the host controller and emulator. In order to evaluate the dependability of the proposed tool, a mechanism has been provided in terms of FoEA (Factors of emulation analysis) and fault injection rate. The FoEA estimates the failure probability of a complete DUT and the failure probability of a specific location inside the DUT which directly affects an output. The designed architecture is initially validated using simulation to verify the functional characteristics. Subsequently, the fault injection campaign has been performed on Kintex-7 FPGA for seven different DUTs. The achieved results have been discussed and compared with state-of-the-art in terms of various performance attributes.INDEX TERMS Dependability, emulation, embedded systems, fault injection, hardware security, Opal Kelly field programmable gate array (FPGA), flexibility.
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