Low <formula formulatype="inline"><tex Notation="TeX">${\rm VDDmin}$</tex></formula> Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations
Abstract:The designs of resistive RAM (ReRAM) macros are limited by 1) a small sensing margin, limited read-, and slow read access time ( ) caused by a high cell-resistance and small cell-resistance-ratio (R-ratio) and 2) poor power integrity and increased energy waste attributable to a large SET dc-current (
) resulting from the wide distribution of write (SET)-times ( ). This study proposes a swing-sample-and-couple (SSC) voltage-mode sense amplifier (VSA) to enable an approximately greater sensing margin for lower a… Show more
“…One can note that this circuit exhibits large area overhead. In other works [33], [34], voltage-mode WT circuits are proposed. These designs are based on the detection of voltage variations that take place on the memory array bit-lines when resistive switching occurs, with possible impact on programming operation-biasing conditions.…”
While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Write Termination (WT) circuits are a potential solution to solve these issues. However, previously reported WT circuits do not demonstrate sufficient reliability. In this work, we propose an industrially-ready WT circuit that was simulated with a RRAM model calibrated on real measurements. We perform extensive CMOS and RRAM variability simulations to extract the actual performances of the proposed WT circuit. Finally, we simulate the effects of the proposed WT circuit with memory traces extracted from real Edge-level data-intensive applications. Overall, we demonstrate 2× to 40× of energy gains at bit level. Moreover, we show from 1.9× to 16.2× energy gains with real applications running depending on the application memory access pattern thanks to the proposed WT circuit.INDEX TERMS RRAM, embedded memories, write termination, memory modeling, low-power design
“…One can note that this circuit exhibits large area overhead. In other works [33], [34], voltage-mode WT circuits are proposed. These designs are based on the detection of voltage variations that take place on the memory array bit-lines when resistive switching occurs, with possible impact on programming operation-biasing conditions.…”
While Resistive Random Access Memories (RRAM) are perceived nowadays as a promising solution for the future of computing, these technologies suffer from intrinsic variability regarding programming voltage, switching speed and achieved resistance values. Write Termination (WT) circuits are a potential solution to solve these issues. However, previously reported WT circuits do not demonstrate sufficient reliability. In this work, we propose an industrially-ready WT circuit that was simulated with a RRAM model calibrated on real measurements. We perform extensive CMOS and RRAM variability simulations to extract the actual performances of the proposed WT circuit. Finally, we simulate the effects of the proposed WT circuit with memory traces extracted from real Edge-level data-intensive applications. Overall, we demonstrate 2× to 40× of energy gains at bit level. Moreover, we show from 1.9× to 16.2× energy gains with real applications running depending on the application memory access pattern thanks to the proposed WT circuit.INDEX TERMS RRAM, embedded memories, write termination, memory modeling, low-power design
“…Process variations, crossbar design and nonlinear selector devices inclusion are the most concerning issues that nowadays limit scope to resistive-switching technologies. To overcome the related design challenges, reliable [1], [2], fast [3], and low-power [1], [3]- [5] writing schemes have been proposed. Although most efforts focus on device to device and cycle to cycle cell variations, temperature is also a critical issue to be addressed in order to ensure the correct behavior of RRAM circuits.…”
Section: Low Resistive State (Lrs) and A High Resistive State (Hrs)mentioning
confidence: 99%
“…Both device to device and cycle to cycle fluctuations can compromise the system reliability. To fight against variability caused problems, systems like [1], [3], [40] provide variability protection during write operations.…”
Abstract-Resistive switching memories (RRAM) are an attractive alternative to non-volatile storage and non-conventional computing systems, but their behavior strongly depends on the cell features, driver circuit and working conditions. In particular, the circuit temperature and the writing voltage scheme become critical issues, determining resistive switching memories performance. These dependencies usually force a design time trade-off among reliability, device endurance and power consumption, and therefore imposing non-flexible functioning schemes and limiting the system performance. In this paper we present a writing architecture that ensures the correct operation no matter the working temperature, and allows the dynamic load of application oriented writing profiles. Thus, taking advantage of more efficient configurations, the system can be dynamically adapted to overcome RRAM intrinsic challenges. Several profiles are analyzed regarding power consumption, temperature-variations protection and operation speed, showing speed-ups near to 700 x compared against other published drivers.
“…Such variations manifest in a large resistance distribution of the memory states, which is particularly problematic for MLC memories that require tight state distributions to reliably pack as many levels as possible into a memory cell. Extensive efforts have been made to address ReRAM device variations through multiple approaches, spanning from device and circuit improvements 17 – 21 , the use of a current compliance during the formation and destruction of the CF 22 – 24 , to higher level write-verify programming schemes based on iterative algorithms to achieve high-precision state tuning 6 , 7 , 9 , 25 . Figure 1 Memory encoding comparison in a two-level cell.…”
Ratio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to $$x^2$$
x
2
at the best case and $$x^{\sqrt{2}}$$
x
2
at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell’s programming time and programming energy by up 5–10$$\times$$
×
, while achieving the same bit error probability.
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