Low-latency modular packet header parser for FPGA

Pus, Viktor; Kekely, Lukáš; Kořenek, Jan

doi:10.1145/2396556.2396571

Cited by 15 publications

(7 citation statements)

References 1 publication

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“…Benacek et al presented an approach to converting P4 to VHDL by using the Parser Graph Representation (PGR) and their HFE M2 architecture in [15,20] and Jeferson et al presented an approach of using templated C++ classes, which can be used to generate RTL code using Xilinx Vivado HLS following a series of graph transformation rounds. These two packet parsers are both organized in a pipeline fashion but of different hardware architectures, and the parsers based on their proposed hardware can process a fairly complex set of headers, as well as achieve 100 Gbps data rate.…”

Section: Packet Parser Solutionsmentioning

confidence: 99%

A Fast Approach for Generating Efficient Parsers on FPGAs

Cao

Zhang

et al. 2019

Symmetry

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The development of modern networking requires that high-performance network processors be designed quickly and efficiently to support new protocols. As a very important part of the processor, the parser parses the headers of the packets—this is the precondition for further processing and finally forwarding these packets. This paper presents a framework designed to transform P4 programs to VHDL and to generate parsers on Field Programmable Gate Arrays (FPGAs). The framework includes a pipeline-based hardware architecture and a back-end compiler. The hardware architecture comprises many components with varying functionality, each of which has its own optimized VHDL template. By using the output of a standard frontend P4 compiler, our proposed compiler extracts the parameters and relationships from within the used components, which can then be mapped to corresponding templates by configuring, optimizing, and instantiating them. Finally, these templates are connected to output VHDL code. When a prototype of this framework is implemented and evaluated, the results demonstrate that the throughputs of the generated parsers achieve nearly 320 Gbps at a clock rate of around 300 MHz. Compared with state-of-the-art solutions, our proposed parsers achieve an average of twice the throughput when similar amounts of resources are being used.

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Section: Packet Parser Solutionsmentioning

confidence: 99%

A Fast Approach for Generating Efficient Parsers on FPGAs

Cao

Zhang

et al. 2019

Symmetry

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“…Nevertheless, as a network monitoring system, it supports distributed and lossless packet level monitoring of Ethernet links for 1 or 10 Gbps. Beside providing sufficient resources for switching and routing at 1 or 10 Gbps, the design of SGA-GPLANAR [10] and SGA-10GED [11] used in SGA-7N includes some special, network monitoring-related requirements, namely -lossless packet capture, -64-bit time-stamping with sub-microsecond resolution, -header-only capture: configurable depth of decoding, -on-the-fly packet parsing by hardware [12], -parameterized packet/flow generator for mass testing [13], [14]. Various applications then require other supported functionalities.…”

Section: B Fpga-based Packet Processingmentioning

confidence: 99%

Time Synchronization Solution for FPGA-based Distributed Network Monitoring

Janky¹,

Varga²

2018

Infocommunications journal

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Distributed network monitoring solutions face various challenges with the increase of line speed, the extending variety of protocols, and new services with complex KPIs. This paper addresses one part of the first challenge: faster line speed necessitates time-stamping with higher granularity and higher precision than ever. Proper, system-wide time-stamping is inevitable for network monitoring and traffic analysis point of view. It is hard to find feasible time synchronization solutions for those systems that have nation-wide, physically distributed probes. Current networking equipment reside in server rooms, and have many legacy nodes. Access to GPS signal is complicated in these places, and Precision Time Protocol (PTP) does not seem to be supported by all network nodes in the near future – so high precision time-stamping is indeed a current problem. This paper suggests a novel, practical solution to overcome the obstacles. The core idea is that in real-life, distributed network monitoring systems operate with a few, finite number of probeclusters, and their site should have a precise clock provided by PTP or GPS somewhere in the building. The distribution of time information within a site is still troublesome, even within a server rack. This paper presents a closed control loop solution implemented in an FPGA-based device in order to minimize the jitter, and compensate the calculated delay.

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“…Source codes can be compiled to a Virtex-7 FPGA device to perform packet parsing at 400 Gbit/s data rate. Viktor Pus et al [2] proposed a parser that is manually optimized for latency and chip area, operating at more than 100 Gbit/s data rate. Their introduced parsing engine provides the classic 5-tuple protocol metadata for each processed packet.…”

Section: Related Workmentioning

confidence: 99%

“…According to the scalability of the parse graph, the engine can be reconfigured at compilation or run time. Publications related to high performance packet parsing [1] [2][3] commonly propose solutions based on reconfigurable parse graphs, in which the identifiable protocolstructure is reconfigurable through offline algorithms using a specified object oriented language. These header definition languages are designed for handling protocol structures with high-level programming tools.…”

Section: Parsing Packet Headersmentioning

confidence: 99%

C-GEP: Adaptive network management with reconfigurable hardware

Orosz

Tóthfalusi

Varga

2015

2015 IFIP/IEEE International Symposium on Integrated Network Management (IM)

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Carrying out network monitoring tasks remains a continuous challenge, partially because the line rate reaches and exceeds 100 Gbit/s. Besides the increasing data rate, the advent of programmable networks necessitates efficient solutions for supporting packet processing tasks in an adaptive way. Introducing a modification of a protocol or any new protocol in such a flexible infrastructure implies a novel management approach incorporating network monitoring equipment with reconfigurable architecture. The requirement for high throughput and high level of reconfiguration together put Field Programmable Gate Array (FPGA) technology into the focus of high performance networking.In this paper, we introduce a programmable, multi-purpose network platform called C-GEP that is based on a reconfigurable architecture. The system consists of two main building blocks: a high performance FPGA-based custom hardware platform and a firmware dedicated for network monitoring. We present the architecture focusing on the system-level integration of specific packet processors. The integration of processing building blocks into one high performance system has great challenges. These are primarily related to specific, limiting factors of system resources -which we discuss also in this paper.

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Low-latency modular packet header parser for FPGA

Cited by 15 publications

References 1 publication

A Fast Approach for Generating Efficient Parsers on FPGAs

A Fast Approach for Generating Efficient Parsers on FPGAs

Time Synchronization Solution for FPGA-based Distributed Network Monitoring

C-GEP: Adaptive network management with reconfigurable hardware

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