Low-latency adiabatic superconductor logic using delay-line clocking

Abstract

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching. However, AQFP logic has somewhat long latency due to the multiphase clocking scheme, in which each logic operation requires a quarter clock cycle. The latency in AQFP logic should be improved in order to design complex digital circuits such as microprocessors. In the present paper, we propose a low-latency clocking scheme for AQFP logic, which we call delay-line clocking. In delay-line clocking, the latency for each logic operation is determined by the propagation delay of the excitation current, which can be much shorter than a quarter clock cycle. Our numerical simulation shows that AQFP gates can operate with a latency of only a few picoseconds. We fabricated an AQFP circuit adopting delay-line clocking using the 10 kA/cm2 Nb high-speed standard process provided by the National Institute of Advanced Industrial Science and Technology. The circuit was demonstrated at 4 GHz with a latency of 10 ps per gate. The above results indicate that delay-line clocking can significantly reduce the latency in AQFP logic.

Adiabatic Quantum-Flux-Parametron: A Tutorial Review

“…8 shows that data stream "01010011" propagates through the buffer chain with a latency of a quarter clock cycle (50 ps at 5 GHz) per gate. This latency is not sufficiently small for some applications; thus, we have also proposed a low-latency clocking scheme, delay-line clocking [67].…”

“…The above results indicate that large-scale, energy-efficient computing systems can be achieved using AQFP logic. Furthermore, we plan to build a more practical MANA by adopting the double-gate process [82] and directly coupled QFP logic [83] for higher circuit density, delay-line clocking [67] for reducing latency, and the high-speed voltage driver [84] and multiblock clock distribution [81] for high-frequency operation.…”

MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices

“…However, AQFP logic is actually an intrinsically fast logic family despite the adiabatic operation. If we consider other clocking schemes, such as delay line clocking [44] or N-phase powerdividing clocking [45], the latency can be reduced substantially by allowing more stages of logic to operate in a singleclock cycle. Such approaches will allow circuit designers and architects more flexibility to implement advanced pipelining techniques.…”

Impedance Design of Excitation Lines in Adiabatic Quantum-Flux-Parametron Logic Using InductEx

“…Furthermore, unlike complementary metal-oxide-semiconductor (CMOS) logic, AQFP gates must be clocked in the order of logic operation with moderate clock skews. We have proposed clocking schemes for AQFP logic [18], [19] to appropriately distribute excitation current in the entire AQFP circuit, by using which we have demonstrated small-to-medium-scale AQFP circuits at GHz-range clock frequencies [14], [19]. To apply the above clock schemes to large-scale AQFP circuits at high clock frequencies, it is required to carefully design the characteristic impedance of excitation lines (i.e., clock paths) so that microwave excitation current is equally applied to each AQFP gate without standing waves.…”