Low–Frequency Noise in Vertically Stacked Si n–Channel Nanosheet FETs

Oliveira, Alberto Vinícius de; Veloso, A.; Claeys, Cor; Horiguchi, N.; Simoen, Eddy

doi:10.1109/led.2020.2968093

Cited by 23 publications

(18 citation statements)

References 31 publications

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“…At the same time, the noise PSD is reduced by at least one decade, demonstrating the potential of this architecture for future CMOS technologies. More detailed results have been reported elsewhere [36].…”

Section: Low-frequency Noise Performancementioning

confidence: 88%

“…Figure 4 represents the area-and frequency-normalized input-referred voltage noise PSD for horizontal, n-and p-channel GAA NSFETs on bulk Si substrates with different gate metal. Predominantly Δn dominated 1/f noise has been observed [36]. No clear impact is found, indicating that there is room for further scaling the thickness of the metal gate in stacked NSs [24].…”

Section: Low-frequency Noise Performancementioning

confidence: 99%

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Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

Simoen

Oliveira

Agopian

et al. 2020

2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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This work reviews the low-frequency noise performance of different flavors of silicon Gate-All-Around Nanowire (NW) (or Nanosheet-NS) transistors. For the horizontal devices, the 1/f-like noise is dominated by the number fluctuations mechanism, so that the Power Spectral Density (PSD) is directly proportional with the trap density in the gate stack. The impact of different process options and device architectures (junctionless versus inversion mode) is discussed. Overall, it is found that the average 1/f noise PSD is reducing going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices and, finally, vertical NW FETs. In the latter case, white noise may dominate the lowfrequency noise spectrum.

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Section: Low-frequency Noise Performancementioning

confidence: 88%

Section: Low-frequency Noise Performancementioning

confidence: 99%

Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

Simoen

Oliveira

Agopian

et al. 2020

2020 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

Self Cite

View full text Add to dashboard Cite

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“…Nevertheless, it seems that the noise in nanowire [271,277,278,279,280,281] and CNT [268,272,274,275,282,283,284,285,286,287,288,289,290,291,292] devices scales according to the rules for mesoscopic devices. This is illustrated in Figure 54.…”

Section: Analysis Of the Ratio K F /R≡a/rmentioning

confidence: 99%

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

2022

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“…The LF noise behavior of NS nMOSFETs has been studied extensively in linear operation, at low VDS (50 mV) [33,[45][46][47]. Emphasis was on the impact of the EWF metal gate.…”

Section: Low-frequency Noisementioning

confidence: 99%

“…Currently, the cryogenic noise performance of pMOSFETs is being evaluated and further measurements down to 10 K are foreseen in the nearby future. nMOSFET [46] Fig. 22 Benchmark of the normalized SV Gab for n-channel silicon devices on either bulk or Silicon-On-Insulator (SOI) wafers: junctionless (JL), inversion mode (IM), finFETs (FF), Gate-All-Around (GAA).…”

Section: Low-frequency Noisementioning

confidence: 99%

Performance Perspective of Gate-All-Around Double Nanosheet CMOS Beyond High-Speed Logic Applications

Simoen

Coelho

Silva

et al. 2022

JICS

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In this review paper, the performance characteristics of Gate-All-Around (GAA) double nanosheet (NS) MOSFETs are described over a broad temperature range, from 78 K to 473 K (200 oC). Emphasis is on the analog operation, showing good potential. Besides the transistor length, the impact of the metal gate Effective Work Function and the vertical distance between the nanosheets has been studied. Among others, a clear Zero Temperature Coefficient (ZTC) gate voltage has been observed that can be modeled by considering the shift with temperature of the threshold voltage and the maximum transconductance. A trade-off has been noticed between the transistor efficiency and the unit gain frequency, whereby the optimal operation point occurs in strong inversion regime. The feasibility of designing simple analog circuits has also been demonstrated. Finally, a detailed investigation of the low-frequency noise behavior yields good values for the flicker noise Power Spectral Density in comparison with other technology nodes.

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Low–Frequency Noise in Vertically Stacked Si n–Channel Nanosheet FETs

Cited by 23 publications

References 31 publications

Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

Horizontal, Stacked or Vertical Silicon Nanowires: Does it Matter from a Low-Frequency Noise Perspective?

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

Performance Perspective of Gate-All-Around Double Nanosheet CMOS Beyond High-Speed Logic Applications

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