Low-Cost Hardware-Sharing Architecture of Fast 1-D Inverse Transforms for H.264/AVC and AVS Applications

Abstract

In this paper, the fast one-dimensional (1-D) algorithms and their hardware-sharing designs for the 1-D 2 x 2, 4 x 4, and 8 x 8 inverse transforms of H.264/AVC and the 1-D 8 x 8 inverse transform of AVS are proposed with the low hardware cost, especially for the multiple decoding applications in China. By sharing the hardware, the proposed 1-D hardware sharing architecture is realized by adding the offset computations, and it is implemented with the pipelined architecture. Thus, the hardware cost of the proposed sharing architecture is smaller than that of the individual and separate designs. With regular modularity, the proposed sharing architecture is suitable to achieve H.264/AVC and AVS signal processing by VLSI implementations

Efficient inverse transform architectures for multi-standard video coding applications

“…The proposed architecture efficiently integrates H.264/AVC, VC-1 and AVS 1-D inverse transforms. The number of gates for the proposed architecture is close to those in [23] and [24], but the proposed architecture can execute all 1-D inverse transforms required in H.264/AVC, VC-1 and AVS decoders.…”

“…The architecture can achieve high throughput with many more logic gates. Two distinct 1-D inverse transforms can be integrated using matrix decompositions with sparse matrices and matrix offset computations [23,24]. However, this method is not suitable for three distinct transforms.…”

“…It uses matrix decompositions with sparse matrices and matrix offset computations. Similarly, a low-cost hardwaresharing architecture for fast 1-D inverse transforms for H.264/AVC and AVS that adds offset computations was designed in [24]. Designs with a hardware-sharing architecture generally have lower hardware costs than those with separate architectures.…”

A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC

“…Other 8 Â 8 transform and quantization designs implemented on FPGAs have been proposed such as the configurable forward and inverse architecture in [15], the simplified forward 8Â 8 transform and quantization architecture, which is capable of processing 64 data/cycle in [16] and its corresponding IP-block in [17], the reduced hardware architecture in [18], which processes pixel by pixel and where the quantization is done without a real multiplier, and the integrated solution in FPGA to perform all transforms and the quantization, which supports luma and chroma for intra-or inter-configurations in [19]. It is worth mentioning other implementations such as the one based on a VLIW+SIMD architecture [20], the unified video CODEC for standards JPEG, MPEG-1/2/4, H.264 and VC-1 [21] or the hardware-sharing designs for the standards H.264 and AVS (developed in China) [22].…”

An unified architecture of all transforms for H.264/AVC codec

“…For decoder use only, [4] [7] implemented a transform processor for 8x8, 4x4 inverse integer transforms, and 4x4 Hadamard transform. 2x2 Hadamard transform even has been embedded into a common architecture in [3] [10]. In [8], an unique kernel for multi-standard video encoder transforms is presented.…”