In this paper, the fast one-dimensional (1-D) algorithms and their hardware-sharing designs for the 1-D 2 x 2, 4 x 4, and 8 x 8 inverse transforms of H.264/AVC and the 1-D 8 x 8 inverse transform of AVS are proposed with the low hardware cost, especially for the multiple decoding applications in China. By sharing the hardware, the proposed 1-D hardware sharing architecture is realized by adding the offset computations, and it is implemented with the pipelined architecture. Thus, the hardware cost of the proposed sharing architecture is smaller than that of the individual and separate designs. With regular modularity, the proposed sharing architecture is suitable to achieve H.264/AVC and AVS signal processing by VLSI implementations
In this letter, the fast one-dimensional (1-D) algorithms and their sharing design for 1-D inverse integer transforms of H.264/AVC and VC-1 are proposed by using the matrix decompositions with the sparse matrices and the matrix offset computations. The computational complexities of the proposed fast 1-D 4 x 4 and 8 x 8 inverse integer transforms for H.264/AVC are the same as those of the previous fast methods. Then the shift operations of the proposed fast 1-D inverse integer transform for VC-1 are equivalent to those of the previous fast method. For playback environments, the video decoder can support the multiple modes, which include H.264/AVC and VC-1 video standards. The proposed hardware sharing architecture requires lower hardware cost than the individual and separate design for the VLSI realization
In this paper, we propose a low multiplier and multiplication complexities 256-point fast Fourier transform (FFT) architecture, especially for WiMAX 802.16a systems. Based on the radix-16 FFT algorithm, the proposed FFT architecture utilizes cascaded simplified radix-24 single-path delay feedback (SDF) structures. The control circuit of the proposed simplified radix-24 SDF FFT architecture is simple.The hardware requirement of the proposed FFT architecture only needs 1 complex multiplier and 56 complex adders for supporting 256-point computations.The computation complexity of multiplications and the hardware complexity of the proposed FFT architecture need less complexity than both complexities of the previous FFT structures in 256-point FFT applications. In hardware verifications, the output throughput rate of our FFT design processes up to 35.5M samples/sec with Xilinx Virtex2 1500 FPGA, and it processes up to 51.5M samples/sec with UIMC 0.18gm standard cell technology. The throughput rate of this implementation is suitable for WiMLAX 802.16a application, whose maximum sample rate is 32MHz.
In this brief, the fast 1-D multiple integer transforms of Windows Media Video 9 (WMV-9/VC-1) are proposed by matrix decompositions, additions, and row/column permutations. Then, the proposed fast 1-D integer transforms are hardware shared, and they can be applied to the 2-D transform scheme. The hardware costs of the proposed fast 1-D and 2-D integer transform designs are smaller than those of the previous individual designs without shares. With the hardware share, the proposed architecture is suitable for the low-cost implementation of the VC-1 codec
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