“…Additionally, the results indicate that, by varying different time parameters of the neural network, the performance of the SNN can be improved, and most probably reach the performance reported for the analog neural network, where the error is in the low single-digit range and the standard deviation at 4.5° (van Schaik and Shamma, 2003, 2004) or even the ASU units with CMOS VLSI design, which is reported to be around 1°–2° (Julian et al, 2006; Goodman and Brette, 2008; Chacon-Rodriguez et al, 2009). As the neural network is very simple it is expected that the performance parameters are advantageous, which we want to investigate and prove an implementation in custom hardware, using a CPLD/FPGA or even new memristive devices (Kyriakides et al, 2012) is feasible.…”