Logic block and routing considerations for a new SRAM-based FPGA architecture

Tavana, Danesh; Yee, W.; Young, Seth; Fawcett, B.K.

doi:10.1109/cicc.1995.518235

Cited by 8 publications

(8 citation statements)

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“…Another major FPGA vendor has added routing resources to the "I/O-channel" that runs between the I/O pads and the logic blocks, at least in part to ensure that fixed I/O pad placement does not impact routability and speed [7]. We define R io to be the ratio between the width of this outermost channel and the width of the other channels.…”

Section: I/o Channelmentioning

confidence: 99%

“…In addition, board-level constraints often force designers to fix the position of an FPGA's I/Os, and some believe that this increases congestion near the chip edges so that the channel between the pads and the logic should be made extra wide. The Xilinx 5000 series FPGA has a wide channel between the pads and logic, at least partially to improve routability when the I/O locations are fixed [7]. In this paper, we determine the best distribution of tracks across an FPGA both when the I/O assignment to pads is unconstrained and when it is fixed in a poor configuration.…”

Section: Introductionmentioning

confidence: 99%

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Directional bias and non-uniformity in FPGA global routing architectures

Betz

Rose

Proceedings of International Conference on Computer Aided Design

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Section: I/o Channelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Directional bias and non-uniformity in FPGA global routing architectures

Betz

Rose

Proceedings of International Conference on Computer Aided Design

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“…Another major FPGA vendor has added routing resources to the "I/O-channel" that runs between the I/O pads and the logic blocks, at least in part to ensure that fixed I/O pad placement does not impact routability and speed [8]. We define R IO to be the ratio of the width of this outermost channel to the width of the other channels.…”

Section: I/o Channelmentioning

confidence: 99%

“…Xilinx 4000 and 5000 series FPGAs have a wide channel between the pads and logic, at least partially to improve routability when the I/O locations are fixed [7,8]. In this paper, we determine the best distribution of tracks across an FPGA both when the I/O assignment to pads is unconstrained and when it is fixed in a poor configuration.…”

Section: Introductionmentioning

confidence: 99%

Effect of the prefabricated routing track distribution on FPGA area-efficiency

Betz

Rose

1998

IEEE Trans. VLSI Syst.

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“…Programmability/reconfigurability of an FPGA is based on an underlying programming technology, which can cause a change in behavior of a prefabricated chip. The main programming technologies used in FPGAs are static random memory (SRAM), flash memory, and antifuse [2][3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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Logic block and routing considerations for a new SRAM-based FPGA architecture

Cited by 8 publications

References 0 publications

Directional bias and non-uniformity in FPGA global routing architectures

Directional bias and non-uniformity in FPGA global routing architectures

Effect of the prefabricated routing track distribution on FPGA area-efficiency

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

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