Effect of the prefabricated routing track distribution on FPGA area-efficiency

Betz, Vaughn; Rose, Jonathan

doi:10.1109/92.711315

Cited by 25 publications

(3 citation statements)

References 12 publications

(16 reference statements)

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“…Betz and Rose [3,4] looked at two issues in interconnect distribution. Using at the segmented model of Figure 1(a), they considered the issue of having different channel densities in different areas of the chip.…”

Section: Uniformitymentioning

confidence: 99%

Interconnect prediction for programmable logic devices

Hutton

2001

Proceedings of the 2001 International Workshop on System-Level Interconnect Prediction

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Classical interconnect prediction would seem to be a perfect fit for the design of programmable logic architectures (PLDs). Yet theoretical models such as those based on Rent's Rule are usually only used for rough estimates in the early stages of an architecture development. In practice, empirical methods (evaluation via many test designs) dominate the evaluation of fitting and performance for PLD architectures.The primary reasons for this gap between theory and practice are that the models are difficult to extend to fixed architectures with hierarchy and heterogeneous resources and that many of the cost metrics are different between gate-arrays and PLDs.In this paper and the accompanying talk I will survey some of the issues with line-count estimation for the design of PLDs. I will point out some of the inherent differences between the way interconnect is used in PLDs and gate arrays which lead to new opportunities in the development of the theory. Some previous results will show how interconnect is typically researched in the PLD community. For an idealized PLD architecture, I will attempt to define a simple line-count estimation model using the classical theory and compare it to results in practice. I will also present some empirical and anecdotal data useful for understanding the issues and pitfalls involved in architecture evaluation.The primary goal of this work is to motivate new directions in the theory of interconnect prediction and interconnect prediction specifically for PLDs.

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Section: Uniformitymentioning

confidence: 99%

Interconnect prediction for programmable logic devices

Hutton

2001

Proceedings of the 2001 International Workshop on System-Level Interconnect Prediction

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“…The routing fabric comprises horizontal and vertical segmented routing channels. In all delay and power comparisons that follow, we set the number of routing tracks to be 15% higher than the minimum required to avoid excessive routing congestion as in [2], [6]- [31]. The design of the connection box (CB) and switch box (SB) follows [2] and the design of the switch point is MUX-based as described in [32] (see Fig.…”

Section: Preliminariesmentioning

confidence: 99%

Exploring FPGA Routing Architecture Stochastically

Lin

Wawrzynek

Gamal

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-This paper proposes a systematic strategy to efficiently explore the design space of field-programmable gate array (FPGA) routing architectures. The key idea is to use stochastic methods to quickly locate near-optimal solutions in designing FPGA routing architectures without exhaustively enumerating all design points. The main objective of this paper is not as much about the specific numerical results obtained, as it is to show the applicability and effectiveness of the proposed optimization approach. To demonstrate the utility of the proposed stochastic approach, we developed the tool for optimizing routing architecture (TORCH) software based on the versatile place and route tool [1]. Given FPGA architecture parameters and a set of benchmark designs, TORCH simultaneously optimizes the routing channel segmentation and switch box patterns using the performance metric of average interconnect power-delay product estimated from placed and routed benchmark designs. Special techniques-such as incremental routing, infrequent placement, multi-modal move selection, and parallelized metric evaluationare developed to reduce the overall run time and improve the quality of results. Our experimental results have shown that the stochastic design strategy is quite effective in co-optimizing both routing channel segmentation and switch patterns. With the optimized routing architecture, relative to the performance of our chosen architecture baseline, TORCH can achieve average improvements of 24% and 15% in delay and power consumption for the 20 largest Microelectronics Center of North Carolina benchmark designs, and 27% and 21% for the eight benchmark designs synthesized with the Altera Quartus II University Interface Program tool. Additionally, we found that the average segment length in an FPGA routing channel should decrease with technology scaling. Finally, we demonstrate the versatility of TORCH by illustrating how TORCH can be used to optimize other aspects of the routing architecture in an FPGA.

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“…A set of datapath-oriented CAD tools, including synthesis, packing, placement, and routing tools, have been developed at the University of Toronto; and in this paper, these tools are used to investigate the area efficiency of the multi-bit routing architecture by experimentally determining the best granularity values and the best amount of bus-based connections for the proposed routing architecture. Extensive research [16] [17] [18] [19] [20] [21] has been conducted in the past in order to Using Bus-Based Connections to Improve Field-Programmable Gate Array Density for Implementing Datapath Circuits determine the best structures for various conventional FPGA routing architectures. These studies have shown the importance of routing architecture on the overall area-efficiency of FPGAs.…”

Section: Introductionmentioning

confidence: 99%

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

Rose

2006

IEEE Trans. VLSI Syst.

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As the logic capacity of Field-Programmable Gate Arrays (FPGAs) increases, they are being increasingly used to implement large arithmetic-intensive applications, which often contain a large proportion of datapath circuits. Since datapath circuits usually consist of regularly structured components (called bit-slices) which are connected together by regularly structured signals (called buses), it is possible to utilize datapath regularity in order to achieve significant area savings through FPGA architectural innovations. This paper describes such an FPGA routing architecture, called the multi-bit routing architecture, which employs bus-based connections in order to exploit datapath regularity. It is experimentally shown that, comparing to conventional FPGA routing architectures, the multi-bit routing architecture can achieve 14% routing area reduction for implementing datapath circuits, which represents an overall FPGA area savings of 10%. This paper also empirically determines the best values of several important architectural parameters for the new routing architecture including the most area efficient granularity values and the most area efficient proportion of bus-based connections.

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Effect of the prefabricated routing track distribution on FPGA area-efficiency

Abstract: In most commercial Field-Programmable Gate Arrays (FPGAs)

Cited by 25 publications

References 12 publications

Interconnect prediction for programmable logic devices

Interconnect prediction for programmable logic devices

Exploring FPGA Routing Architecture Stochastically

Using bus-based connections to improve field-programmable gate-array density for implementing datapath circuits

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