Local $V_{\rm th}$ Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation

Sugii, Nobuyuki; Tsuchiya, R.; Ishigaki, Takashi; Morita, Yusuke; Yoshimoto, Hiroyuki; Kimura, S.

doi:10.1109/ted.2010.2040664

Cited by 107 publications

(29 citation statements)

References 26 publications

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“…In this work, the power reconfigurable FPGA is designed on the 65-nm SOTB CMOS technology [16] which is the advanced SOI technology with ultra-thin buried-oxide (BOX). The effective energy reduction in the SOTB CMOS technology is recently reported for such new applications as en- ergy harvesting sensor network systems, and long lasting wearable computers [17].…”

Section: Adoption Of Customization Design Rulementioning

confidence: 99%

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology

Hioki

Koike

2016

IEICE Trans. Inf. & Syst.

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SUMMARYA Field Programmable Gate Array (FPGA) with finegrained body biasing shows satisfactory static power reduction. Contrarily, the FPGA incurs high overhead because additional body bias selectors and electrical isolation regions are needed to program the threshold voltage (V t ) of elemental circuits such as MUX, buffer and LUT in the FPGA. In this paper, low overhead design of FPGA with fine-grained body biasing is described. The FPGA is designed and fabricated on 65-nm SOTB CMOS technology. By not only adopting a customized design rule specifying that reliability is verified by TEGs but downsizing a body bias selector, the FPGA tile area becomes small by 39% compared with the conventional design, resulting in 900 FPGA tiles with 4,4000 programmable V t regions. In addition, the chip performance is evaluated by implementing 32-bit binary counter in the supply voltage range of 0.5V from 1.2V. The counter circuit operates at a frequency of 72MHz and 14MHz with the supply voltage of 1.2V and 0.5V respectively. The static power saving of 80% in elemental circuits of the FPGA at 0.5-V supply voltage and 0.5-V reverse body bias voltage is achieved in the best case. In the whole chip including configuration memory and body bias selector in addition to elemental circuits, effective static power reduction around 30% is maintained by applying 0.3-V reverse body bias voltage at each supply voltage. key words: FPGA, programmable V t , body biasing, static power

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Section: Adoption Of Customization Design Rulementioning

confidence: 99%

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology

Hioki

Koike

2016

IEICE Trans. Inf. & Syst.

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“…Therefore, RDF-induced V TH fl uctuations are well suppressed. 16 However, the potential fl uctuations due to donors in the source and drain extensions (S/D-RDF) lead to large fl uctuations in the source/drain access resistance and translate to an increase in the on-current variability, as has been recently shown theoretically and experimentally. 17,18 Additionally, the S/D-RDF implies a local modulation of the channel length, and therefore one may expect RDF to impact DIBL fl uctuations too.…”

Section: Qualitative Insight From Modelling and Simulationmentioning

confidence: 93%

Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

Markov

Cheng

Zain

et al. 2014

Silicon-on-Insulator (SOI) Technology

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“…As a result, by applying this to the SRAM cells, the static noise margins (SNMs) are improved by adding back feedback from the back gate to the front gate [10]. Moreover, SOTB has the smallest threshold voltage variability among bulk MOS, due to its low-dose channel [12]. Figure 1b shows the SPICE simulation results of on-currents and off-currents to the back-bias voltage for the range from 0 V to −1.0 V in a bulk NMOS transistor and an SOTB NMOS transistor in 65-nm technology.…”

Section: Silicon On Thin Buried Oxide (Sotb) Transistormentioning

confidence: 99%

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

Hioki

Kobayashi

et al. 2014

JLPEA

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Field programmable gate arrays (FPGAs) are one of the most widespread reconfigurable devices in which various functions can be implemented by storing circuit connection information and logic values into configuration memories. One of the most important issues in the modern FPGA is the reduction of its static leakage power consumption. Flex Power FPGA, which has been proposed to overcome this problem, uses a body biasing technique to implement the fine-grained threshold voltage (Vt) programmability in the FPGA. A low-Vt state can be assigned only to the component circuits along the critical path of the application design mapped on the FPGA, so that the static leakage power consumption can be reduced drastically. Flex Power FPGA is an important application target for the SOTB OPEN ACCESSJ. Low Power Electron. Appl. 2014, 4 189(silicon on thin buried oxide) device, which features a wide-range body biasing ability and the high sensitivity of Vt variation by body biasing, resulting in a drastic subthreshold leakage current reduction caused by static leakage power. In this paper, the Flex Power FPGA test chip is fabricated in SOTB technology, and the functional test and performance evaluation of a mapped 32-bit binary counter circuit are performed successfully. As a result, a three orders of magnitude static leakage reduction with a bias range of 2.1 V demonstrates the excellent Vt controllability of the SOTB transistors, and the 1.2 V bias difference achieves a 50× leakage reduction without degrading speed.Keywords: field programmable gate array (FPGA); static leakage power reduction; fine-grained body biasing; silicon on thin buried oxide (SOTB)

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Local $V_{\rm th}$ Variability and Scalability in Silicon-on-Thin-BOX (SOTB) CMOS With Small Random-Dopant Fluctuation

Cited by 107 publications

References 26 publications

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology

Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology

Understanding variability in complementary metal oxide semiconductor (CMOS) devices manufactured using silicon-on-insulator (SOI) technology

SOTB Implementation of a Field Programmable Gate Array with Fine-Grained Vt Programmability

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