Abstract:We report on a new roadblock which will limit the gate oxide thickness scaling of MOSFETs. It is found that statistical distribution of direct tunnel leakage current through 1.2 to 2.8 nm thick gate oxides induces significant fluctuations in the threshold voltage and transconductance when the gate oxide tunnel resistance becomes comparable to gate poly-Si resistance. By calculating the measured tunnel current based on multiple scattering theory, it is shown that the device characteristics fluctuations will be … Show more
“…[25][26][27][28] The residual minimization method of direct inversion in the iterative subspace (RMM-DIIS) was used to calculate the ground state of electrons. 29,30 More precisely, Si atom 3s 2 2 states, and H atom 1s 1 state were treated as valence wave functions. The cutoff energy was 500 eV, and the k-points mesh was 2 × 2 × 1, using MonkhorstPack for the slab superstructure with a 20 Å vacuum layer.…”
Section: Calculation Detailsmentioning
confidence: 99%
“…However, the direct tunneling of electrons through the gate oxide becomes substantial for silicon oxide (SiO 2 ) layers below 1.2 nm thick. 2 Recently, high dielectric constant (high-k) materials have replaced SiO 2 as gate oxide materials. 3 Their necessary capacitance can be achieved with the thicker film, thereby avoiding the direct tunneling problem.…”
We studied the reaction of tri-methylaluminum (TMA) on hydroxyl (OH)-terminated Si (001) surfaces for the initial growth of aluminum oxide thin-films using density functional theory. TMA was adsorbed on the oxygen atom of OH due to the oxygen atom's lone pair electrons. The adsorbed TMA reacted with the hydrogen atom of OH to produce a di-methylaluminum group (DMA) and methane with an energy barrier of 0.50 eV. Low energy barriers in the range of 0 -0.11 eV were required for DMA migration to the inter-dimer, intra-dimer, and inter-row sites on the surface. A unimethylaluminum group (UMA) was generated at each site with low energy barriers in the range of 0.21 -0.25 eV. Among the three sites, the inter-dimer site was the most probable for UMA formation.
“…[25][26][27][28] The residual minimization method of direct inversion in the iterative subspace (RMM-DIIS) was used to calculate the ground state of electrons. 29,30 More precisely, Si atom 3s 2 2 states, and H atom 1s 1 state were treated as valence wave functions. The cutoff energy was 500 eV, and the k-points mesh was 2 × 2 × 1, using MonkhorstPack for the slab superstructure with a 20 Å vacuum layer.…”
Section: Calculation Detailsmentioning
confidence: 99%
“…However, the direct tunneling of electrons through the gate oxide becomes substantial for silicon oxide (SiO 2 ) layers below 1.2 nm thick. 2 Recently, high dielectric constant (high-k) materials have replaced SiO 2 as gate oxide materials. 3 Their necessary capacitance can be achieved with the thicker film, thereby avoiding the direct tunneling problem.…”
We studied the reaction of tri-methylaluminum (TMA) on hydroxyl (OH)-terminated Si (001) surfaces for the initial growth of aluminum oxide thin-films using density functional theory. TMA was adsorbed on the oxygen atom of OH due to the oxygen atom's lone pair electrons. The adsorbed TMA reacted with the hydrogen atom of OH to produce a di-methylaluminum group (DMA) and methane with an energy barrier of 0.50 eV. Low energy barriers in the range of 0 -0.11 eV were required for DMA migration to the inter-dimer, intra-dimer, and inter-row sites on the surface. A unimethylaluminum group (UMA) was generated at each site with low energy barriers in the range of 0.21 -0.25 eV. Among the three sites, the inter-dimer site was the most probable for UMA formation.
“…Reducing the oxide layer thickness will lead to problems of tunneling leakage current through the source/drain and substrate. [1,2] Defect may also occur in thin oxide film. The gate oxide leakage is observed in MOSFET systems.…”
Abstract. In this work, we investigate the electrical properties of oxide layer in the metal-oxide semiconductor field effect transistor (MOSFET). The thickness of oxide layer is proportional to square root of oxidation time. The feature of oxide layer thickness on the growth time is consistent with the Deal-Grove model effect. From the current-voltage measurement, it is found that the threshold voltages (Vt) for MOSFETs with different oxide layer thicknesses are proportional to the square root of the gate-source voltages (Vgs). It is also noted that threshold voltage of MOSFET increases with the thickness of oxide layer. It indicates that the bulk effect of oxide dominates in this MOSFET structure.
“…Quantum-mechanical tunneling through ultrathin gate oxides and carrier-mobility degradation due to high channel doping are issues which place limitations on bulk-Si MOSFET scaling, however [1], [2]. Recently, new transistor structures such as the ultrathin body (UTB) MOSFET and double-gate FinFET have been proposed to improve the scalability of the MOSFET, for CMOS technology generations beyond the 65-nm technology node [3].…”
Abstract-Damage-free sputter deposition and highly selective dry-etch processes have been developed for molybdenum (Mo) metal gate technology, for application to fully depleted silicon-on-insulator ( devices such as the ultrathin body (UTB) MOSFET and double-gate FinFET. A plasma charge trap effectively eliminates high-energy particle bombardment during Mo sputtering; hence the gate-dielectric integrity (TDDB, BD ) is significantly improved and the field-effect mobility in Mo-gated MOSFETs follows the universal mobility curve. The effects of etch process parameters such as chlorine (Cl 2 ) and oxygen (O 2 ) gas flow rate, and source and bias radio frequence powers, were investigated in order to optimize the Mo etch rate and selectivity to SiO 2 . A highly selective etch process was successfully applied to pattern Mo gate electrodes for UTB MOSFETs and FinFETs without leaving any residue or stringers. Measured electrical characteristics and physical analysis results are discussed.Index Terms-Complementary metal-oxide-semiconductor (CMOS), dry etching, FinFET, fully depleted silicon-on-insulator (FD SOI), molybdenum metal gate, sputter, ultrathin body.
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