Effect of Oxide Layer in Metal-Oxide-Semiconductor Systems

Fan, Jung-Chuan; Lee, Shih-Fong

doi:10.1051/matecconf/20166706103

Cited by 12 publications

(3 citation statements)

References 6 publications

(5 reference statements)

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“…As the gate voltage is increased, the electric field in the oxide widens, finally causing oxide breakdown [35,37]. It's also important to note that the MOSFET threshold voltage increases with oxide layer thickness [7]. Therefore, it is essential to thermally develop a thick SiO2 gate (> 50 nm) with great quality for high-power devices.…”

Section: Resultsmentioning

confidence: 99%

“…Today, a high-quality, moderately thick gate oxide is needed for high-power technology in order to handle a 15 V of gate voltage (VG). According to reports, the Fowler-Nordheim tunnelling gate, which is a significant current flow that happens when MOSFETs are operated at high gate voltages, tends to damage the oxide [5,6], especially in thin oxide films [7]. Therefore, a thermally grown thick silicon dioxide (SiO2) gate with good quality is essential for high-power device applications.…”

Section: Introductionmentioning

confidence: 99%

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The Modelling of SiC Gate Oxide Thickness based on Thermal Oxidation Temperatures and Durations for High-Voltage Applications

Hashim

Poobalan²,

Zakaria³

et al. 2023

Trends Sci

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This research has shown that the oxide thickness for silicon carbide (SiC) based wide materials can be predicted using regression techniques in wet/dry nitrided or wet/dry non-nitrided thermal oxidation process conditions for high voltage applications by employing 2 different regression techniques: Polynomial and linear regression. The R-squared (R2) and Mean Absolute Percentage Error (MAPE) techniques are used to evaluate the regression models. Furthermore, this work investigates and presents a calculation of gate oxide thickness that is correlated to gate voltage ranges for high voltage applications. In this work, the thermal oxidation process environment is classified into 3 different processing conditions: conventional (dry and wet), dry nitrided (NO,N2O), and wet nitrided (HNO3 vapour). The findings from this study showed that wet oxidation combined with nitrided elements can produce thicker and better-quality gate oxide as compared to conventional dry and wet oxidation techniques. The outcome of this work clearly shows that gate oxide thickness may be derived from silicon carbide-based wide-bandgap materials utilizing linear and polynomial approaches using thermal oxidation durations at different temperatures for high-power applications. The regression models and formulations produced in this work are expected to aid the researchers in determining appropriate oxide thickness under practicable process conditions, with the exception of real thermal oxidation process conditions. Hence, the outcome of this work is expected to save the processing time, material, and cost of the power semiconductor device fabrication technology, mainly for high voltage applications. HIGHLIGHTS Regression approaches are being used to determine the oxide thickness (Tox) for SiC-based broad materials in nitrided and non-nitrided thermal oxidation process conditions for high-voltage applications The regression models are assessed using the R-squared (R2) and Mean Absolute Percentage Error (MAPE) approaches The results of this work are anticipated to reduce processing time, material requirements, and manufacturing costs for power semiconductor devices used in high-voltage applications GRAPHICAL ABSTRACT

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The Modelling of SiC Gate Oxide Thickness based on Thermal Oxidation Temperatures and Durations for High-Voltage Applications

Hashim

Poobalan²,

Zakaria³

et al. 2023

Trends Sci

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“…In order to minimize the parasitic series resistance caused by insulting Al 2 O 3 film, the optimal film thickness is typically limited to be around 1.5 nm. , This leads to a smaller tunnel barrier width that can ultimately benefit free carriers moving between layers. , Nevertheless, inhomogeneous film coverage with morphological defects (e.g., pinholes) are usually observed at such a small thickness. , This phenomenon was supported by evaluating the surface morphology of Al 2 O 3 film formed by the oxidation of thermally evaporated 1.5 nm Al layer (hereafter referred to as naturally oxidized Al 2 O 3 ), as pinhole-containing surface morphology (marked with yellow circles in Figure b) with root-mean-square roughness of 1.2 nm was observed (Figure a and b). It is worth noting that the nanoscale defects within Al 2 O 3 film can act as electrical leakage paths, which is detrimental to the device performance. Importantly, taking the unique advantages of ALD film such as excellent conformability and uniformity over large areas, low deposition temperature, and precise control of film thickness, ultrathin Al 2 O 3 film (thickness = 1.5 nm) with high-quality pinhole-free characteristics was attained, revealing relatively smooth surface (root mean-square roughness = 0.4 nm) and low contrast in phase image (Figure c and d).…”

Section: Results and Discussionmentioning

confidence: 99%

Interface Engineering for High-Performance and Stable Hybrid Perovskite Shadow-Effect Energy Generator

2023

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Photovoltaic cells generally suffer a loss of output power due to ubiquitous shadows, which can greatly limit their practical use, especially in metropolitan regions. Very recently, a shadow-effect energy generator (SEG), a new platform that can scavenge energy under shadow conditions, has been demonstrated. In contrast to previously reported SEG based on silicon system, in this study, for the first time, methylammonium lead iodide (MAPbI 3 ) perovskite-based flexible SEG with high-performance and long-term stability is achieved through interface engineering strategy, involving inclusion of atomic-layer-deposited (ALD)layers between the electrode and perovskite layer. The incorporation of the ALD Al 2 O 3 film effectively suppresses the mobile iodide ioncaused electrode corrosion problem and ensures the formation of a Schottky potential barrier. On the other hand, the inclusion of DPP-CNTVT layer can passivate the defects within the perovskite layer and facilitate charge generation and extraction. With all these advantages, the resulting flexible SEG devices exhibit remarkable power density up to 18.22 μW cm −2 under half-in-shadow conditions, which can light up 7 light-emitting diodes and a calculator. To the best of our knowledge, this is the first successful demonstration of perovskite SEG devices, and the power density achieved herein even outperforms that of state-of-the-art siliconbased SEG measured under the same condition. Additionally, through the use of UV-cured epoxy/fluorinated polymer poly(perfluoro(1-butenyl vinyl ether) (CYTOP) bilayer film as the encapsulation layer, long-term stable SEG devices can be realized. Importantly, our strategy has shown great promise for extending the applicability of SEG to flexible semitransparent power sources and self-powered photodetectors. This work provides important guidelines for the exploitation of high-performance and stable perovskite SEG through interface engineering, which sets a new milestone in this field and presents a significant step toward the practical applications of this emerging technology.

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The impact of a recessed Δ-shaped gate in a vertical CAVET AlGaN/GaN MIS-HEMT for high-power low-loss switching applications

Danielraj¹,

Deb²,

Mohanbabu

et al. 2021

J Comput Electron

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A Δ-shaped gate GaN-based E-mode vertical current-aperture vertical electron transistor (CAVET) device with a borondoped current block layer (B-CBL) on an n + GaN substrate is proposed, designed, and demonstrated herein. Enhancementmode (E-mode) operation is achieved in the proposed device by introducing a 1-μm-thick p-GaN CBL layer into the recessed Δ-shaped gate of the metal-insulator-semiconductor (MIS) high-electron-mobility transistor (HEMT) structure. The device exhibits a threshold voltage of 6.76 V, a drain current saturation of I ds,sat = 3.44 kA/cm 2 , a transconductance of g m = 783.42 S/cm 2 , and an ON/OFF current ratio > 10 10 A/ cm 2 . The breakdown voltage in the OFF-state (V BR,OFF ) shows a maximum of 1590 V and a minimum of 1513 V for a CBL layer thickness (t B-CBL ) of 0.2 and 1 µm at a gate bias of 0 V. The lowest ON-state resistance (R ON ) achieved is 1.24 Ω cm 2 , accompanied by a low gate current of I g,L < 10 -9 and a drain leakage current of I d,L < 10 -8 A/mm. The device exhibits high-frequency performance with peak f t and f max values of 5.12 GHz and 36.8 GHz, respectively, as measured from two-port Y parameters with an Si 3 N 4 thickness (t Si3N4 ) of 40 nm and a recessed penetration depth (t penetration ) of 0.2 µm at V ds = 10 V. Finally, the performance of the vertical CAVET AlGaN/GaN MIS-HEMT power switching device with a boron-doped GaN CBL is analyzed using an ultralow-loss boost converter circuit. The results of the analysis of the demonstrated device indicate that it is a suitable candidate for use in high-power low-loss switching applications.

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Effect of Oxide Layer in Metal-Oxide-Semiconductor Systems

Cited by 12 publications

References 6 publications

The Modelling of SiC Gate Oxide Thickness based on Thermal Oxidation Temperatures and Durations for High-Voltage Applications

The Modelling of SiC Gate Oxide Thickness based on Thermal Oxidation Temperatures and Durations for High-Voltage Applications

Interface Engineering for High-Performance and Stable Hybrid Perovskite Shadow-Effect Energy Generator

The impact of a recessed Δ-shaped gate in a vertical CAVET AlGaN/GaN MIS-HEMT for high-power low-loss switching applications

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