Molybdenum Gate Technology for Ultrathin-Body MOSFETs and FinFETs

Abstract

Abstract-Damage-free sputter deposition and highly selective dry-etch processes have been developed for molybdenum (Mo) metal gate technology, for application to fully depleted silicon-on-insulator ( devices such as the ultrathin body (UTB) MOSFET and double-gate FinFET. A plasma charge trap effectively eliminates high-energy particle bombardment during Mo sputtering; hence the gate-dielectric integrity (TDDB, BD ) is significantly improved and the field-effect mobility in Mo-gated MOSFETs follows the universal mobility curve. The effects of etch process parameters such as chlorine (Cl 2 ) and oxygen (O 2 ) gas flow rate, and source and bias radio frequence powers, were investigated in order to optimize the Mo etch rate and selectivity to SiO 2 . A highly selective etch process was successfully applied to pattern Mo gate electrodes for UTB MOSFETs and FinFETs without leaving any residue or stringers. Measured electrical characteristics and physical analysis results are discussed.Index Terms-Complementary metal-oxide-semiconductor (CMOS), dry etching, FinFET, fully depleted silicon-on-insulator (FD SOI), molybdenum metal gate, sputter, ultrathin body.

DC self-heating effects modelling in SOI and bulk FinFETs

“…Its vertical cross-section (through the gate) has been sketched in Fig. 1(b), and the corresponding geometrical parameters, taken from [1,5] and [14][15][16], are listed in Table 1.…”

Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology

“…They lead into the source/drain regions in the fin where the dopant concentration gradually decreases progressing towards the relatively undoped body region, causing either an overlap (L OV ) or an underlap (L UN ). The V th of FinFETs is typically tuned by directly adjusting the workfunction of the gate material [14]. Accounting for temperature effects, we performed hydrodynamic mixed-mode device-circuit simulation on carefully defined meshes (for excellent convergence) and invoked the density gradient model for incorporating quantum effects in a thin fin.…”

Double gate underlap FinFET device optimization and application in SRAM design at 15 nm

“…Additionally, metal gates have low resistance and work function tuning of various metal compounds (e.g. [11], [12]) is an attractive technique for setting the device threshold voltage without modifying the channel doping.…”