2016
DOI: 10.1088/0022-3727/49/11/115104
|View full text |Cite
|
Sign up to set email alerts
|

Light-bias coupling erase process for non-volatile zinc tin oxide TFT memory with a nickel nanocrystals charge trap layer

Abstract: A nonvolatile charge trapping memory is demonstrated on a thin film transistor (TFT) using a solution processed ultra-thin (~7 nm) zinc tin oxide (ZTO) semiconductor layer with an Al2O3/Ni-nanocrystals (NCs)/SiO2 dielectric stack. A positive threshold voltage (V TH) shift of 7 V is achieved at gate programming voltage of 40 V for 1 s but the state will not be erased by applying negative gate voltage. However, the programmed V TH shift can be expediently erased by applying a … Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
3
1
1

Citation Types

0
8
0

Year Published

2017
2017
2022
2022

Publication Types

Select...
7

Relationship

1
6

Authors

Journals

citations
Cited by 10 publications
(8 citation statements)
references
References 20 publications
0
8
0
Order By: Relevance
“…This hysteresis window is relatively large compared to that of the conventional metal-oxide-semiconductor eld-effect transistor (MOSFET) memory device with NPs inserted between the gate insulators. 17 The observed hysteresis of transfer characteristics is a clear indication that the charge carriers are trapped at the AgNWs layer. The wide hysteresis window in the memory device based on Hf-doped ZnO TFT with AgNWs could be due to Hf occupancy at either the interstitial or substitutional position of the Zn sites in the ZnO matrix.…”
Section: Resultsmentioning
confidence: 96%
“…This hysteresis window is relatively large compared to that of the conventional metal-oxide-semiconductor eld-effect transistor (MOSFET) memory device with NPs inserted between the gate insulators. 17 The observed hysteresis of transfer characteristics is a clear indication that the charge carriers are trapped at the AgNWs layer. The wide hysteresis window in the memory device based on Hf-doped ZnO TFT with AgNWs could be due to Hf occupancy at either the interstitial or substitutional position of the Zn sites in the ZnO matrix.…”
Section: Resultsmentioning
confidence: 96%
“…Defects within the AZO nanoparticle layer will significantly enhance the charge trapping effect, as conceived from the shift of the I D – V G characteristic curves shown in Figure and the hysteresis transfer characteristics in Figure S3 (Supporting Information). The mechanism under the photoresponse enhancement is associated with the light-assisted charge detrapping process, as proposed in our previous study . The light illumination will ionize oxygen vacancies (V O ) to positively charged oxygen vacancies (V O + and V O ++ ) in the ZTO layer.…”
Section: Resultsmentioning
confidence: 79%
“…The mechanism under the photoresponse enhancement is associated with the light-assisted charge detrapping process, as proposed in our previous study. 14 The light illumination will ionize oxygen vacancies (V O ) to positively charged oxygen vacancies (V O + and V O ++ ) in the ZTO layer. Consequently, the positively charged oxygen vacancies in ZTO and the trapped electrons (negatively charged) will build an internal electric field, which will offer a driving force for the trapped electrons to tunnel to ZTO, and the charges are thus detrapped.…”
Section: Resultsmentioning
confidence: 99%
“…Oxide-semiconductor-based memory is an ideal candidate for future transparent or flexible devices because oxide semiconductors offer more transparency and mechanical flexibility than typical silicon semiconductors. In 2016, Li et al implemented ZTO TFT-based nonvolatile charge trapping memories (CTMs) using nickel nanocrystals as charge trapping regions [ 73 ]. In the fabricated optical memory, the V TH shifted up to 7 V with a positive gate programming voltage of 40 V, but the programmed state was not erased at a negative gate voltage.…”
Section: Zto Film and Applicationsmentioning
confidence: 99%