Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs

Mangalagiri, Prasanth; Narayanan, Vijaykrishnan

doi:10.1109/isvlsi.2009.42

Cited by 3 publications

(2 citation statements)

References 18 publications

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“…Longer measurement periods may require longer times to read the total number of oscillations. The decrement of MTTF rate becomes faster since it is exponentially related to the temperature as stated in the following equation [62]:

normalMTT F_{e m} \propto \frac{{()(, J)}^{- n} e^{E_{a E M} / k T}}{L_{eff}}

where J is the current density in the interconnect, n and

E_{a m}

are constants, depending on the type of metal interconnect used.

L_{eff}

is the effective length of the wire across which the current density is measured, k is the Boltzmann's constant and T is the absolute temperature of the wire in degrees kelvin.…”

Section: Results and Analysismentioning

confidence: 99%

See 1 more Smart Citation

Delay performance due to thermal variation on field‐programmable gate array via the adoption of a stable ring oscillator

Jaafar

Soin²,

Hatta³

et al. 2019

IET Computers & Digital Techniques

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Thermal issues are rapidly evolving in the field-programmable gate arrays (FPGAs) and are being intensely studied as these issues appear to significantly affect the delay performance of FGPAs. A ring oscillator has been widely used as a digital temperature sensor to sense this thermal effect on FPGAs. The delay generated by the ring oscillator will vary depending on the temperature environment due to negative bias temperature instability, hot carrier injection and electromigration. It is therefore critical to adopt an accurate ring oscillator design to effectively measure the delay in FGPAs. In this study, a digital temperature sensor with a stable ring oscillator is proposed. Measurement periods of 512 and 4096 clock cycles have been implemented and the relationship between temperature, delay and total count has been established. The results show that as the temperature increases to 100°C, the delay decreases by 3.99 and 33.98% for 512 and 4096 clock cycles, respectively. It has been found that in order to reduce the degradation effect on the Virtex-6 FPGA, adopting a measurement period of 512 clock cycles is the best method. The measured data is successfully validated through a set of simulations. Thus, it may benefit a system designer and industrial player, especially in designing temperature-based FPGAs.

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normalMTT F_{e m} \propto \frac{{()(, J)}^{- n} e^{E_{a E M} / k T}}{L_{eff}}

where J is the current density in the interconnect, n and

E_{a m}

are constants, depending on the type of metal interconnect used.

L_{eff}

is the effective length of the wire across which the current density is measured, k is the Boltzmann's constant and T is the absolute temperature of the wire in degrees kelvin.…”

Section: Results and Analysismentioning

confidence: 99%

Section: Clock Cycles Periodmentioning

confidence: 99%