Performance Failure Prediction Using Built-In Delay Sensors in FPGAs

Bexiga, V.; Leong, C.; Semião, J.; Teixeira, I.C.; Teixeira, J.P.; Valdés, M.D.; Freijedo, J.; Rodríguez-Andina, Juan J.; Vargas, F.

doi:10.1109/fpl.2011.61

Cited by 8 publications

(6 citation statements)

References 15 publications

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“…TDFs are avoided by keeping a guard-band on the setup time. On the other hand, DVS [Das et al 2006[Das et al , 2009] relies on increasing the voltage source to increase the drain current, thus compensating for performances losses. Another approach to increase drain current capability consists of modifying the body bias voltage, as outlined by Fuketa et al [2012].…”

Section: Background and Related Workmentioning

confidence: 99%

“…Previous publications addressing aging phenomena and late transitions effects in FPGA-based systems mainly focus on TDFs detection [Li and Lach 2007;Amouri and Tahoori 2011;Valdes-Pena et al 2013], requiring significant manual design efforts to obtain aging-aware designs [Bexiga et al 2011]. Only a few attempts to exploit Dynamic Partial Reconfiguration (DPR) available in several FPGA architectures to design adhoc countermeasures against TDFs have been proposed [Di Carlo et al 2012;Kameda et al 2012].…”

Section: Introductionmentioning

confidence: 99%

“…Several efficient solutions spanning from Dynamic Frequency Scaling (DFS) [Fukazawa et al 2008] to Dynamic Voltage Scaling (DVS) [Das et al 2006] have been proposed in the scientific literature and are applied to real designs. However, when considering SoPCs, the use of FPGA-specific facilities to countermeasure TDFs is a topic that has not been fully investigated to date.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Satta

Carlo

Gambardella

Prinetto

et al. 2015

ACM Trans. Reconfigurable Technol. Syst.

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Dependability issues due to nonfunctional properties are emerging as a major cause of faults in modern digital systems. Effective countermeasures have to be developed to properly manage their critical timing effects. This article presents a methodology to avoid transition delay faults in field-programmable gate array (FPGA)-based systems, with low area overhead. The approach is able to exploit temperature information and aging characteristics to minimize the cost in terms of performances degradation and power consumption. The architecture of a hardware manager able to avoid delay faults is presented and analyzed extensively, as well as its integration in the standard implementation design flow.

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Section: Background and Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Satta

Carlo

Gambardella

Prinetto

et al. 2015

ACM Trans. Reconfigurable Technol. Syst.

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“…Almost none of these approaches addresses the concerns about how difficult it may be to introduce monitoring at different stages, and in some cases, sensors make use of scarce resources (such as system clocks in [5] or DCMs in [4]). …”

Section: Introductionmentioning

confidence: 99%

“…Current work on this field includes the usage of ring oscillators [3], launch and capture circuitry [1], configurable clock sources [4], or clocked delay chains [5] in order to measure temperature, aging, clock variability, etc. Almost none of these approaches addresses the concerns about how difficult it may be to introduce monitoring at different stages, and in some cases, sensors make use of scarce resources (such as system clocks in [5] or DCMs in [4]).…”

Section: Introductionmentioning

confidence: 99%

A monitoring infrastructure for FPGA self-awareness and dynamic adaptation

Osuna

Marcos

Ituero

et al. 2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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Abstract-Variabilities associated with CMOS evolution affect the yield and performance of current digital designs. FPGAs, which are widely used for fast prototyping and implementation of digital circuits, also suffer from these issues. Proactive approaches start to appear to achieve self-awareness and dynamic adaptation of these devices. To support these techniques we propose the employment of a multi-purpose sensor network. This infrastructure, through adequate use of configuration and automation tools, is able to obtain relevant data along the life cycle of an FPGA. This is realised at a very reduced cost, not only in terms of area or other limited resources, but also regarding the design effort required to define and deploy the measuring infrastructure. Our proposal has been validated by measuring inter-die and intra-die variability in different FPGA families.

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