Leveraging Data Promotion for Low Power D-NUCA Caches

Abstract

D-NUCA caches are cache memories that, thanks to banked organization, broadcast search and promotion/demotion mechanism, are able to tolerate the increasing wire delay effects introduced by technology scaling. As a consequence, they will outperform conventional caches (UCA, Uniform Cache Architectures) in future generation cores. Due to the promotion/demotion mechanism, we observed that the distribution of hits across the ways of a D-NUCA cache varies across applications as well as across different execution phases within a single application. In this work, we show how such a behavior can be leveraged to improve the D-NUCA power efficiency as well as to decrease its access latency. In particular, we propose: 1) A new microarchitectural technique to reduce the static power consumption of a D-NUCA cache by dynamically adapting the number of active (i.e. powered-on) ways to the need of the running application; our evaluation shows that a strong reduction of the average number of active ways (37.1%) is achievable, without significantly affecting the IPC (-2.25%), leading to a resultant reduction of the Energy Delay Product (EDP) of 30.9%. 2) A strategy to estimate the characteristic parameters of the proposed technique. 3) An evaluation of the effectiveness of the proposed technique in the multicore environment

A survey of architectural techniques for improving cache power efficiency

“…without die-stacking) cache and also block-based and page-based 3D stacked DRAM cache designs. [19], [31], [39], [42], [45], [52], [53], [79] state-destroying [13], [20], [23]- [25], [29], [43], [70], [80]- [86] either or both [30], [41], [87], [88] Reconfig. granularity way-level [20], [52], [53], [56], [89]- [93] set-level (or bank-level) [43], [92] hybrid (set and way) level [23], [81], [94] cache block-level [13], [29], [31], [41], [42], [45], [78]- [80], [84], [88] cache sub-block level [86], cache color level [24]- [26] cache sub-array level [82] Reconfig.…”

“…Fixed large interval [13], [20], [23]- [25], [42], [43], [52], [81], [82], [84], [92], [94] variable interval [29], [79], [80] continuous reconfig. [30], [31], [41], [45], [52], [53], [78], [86], [87] Basic property on Inclusion property of cache hierarchies [30] which ESTs work temporal locality [13], [29], [31], [41], [42], [45], [48], [52], [79], [80], [84], [86] varying working set size [23]- [26], [43], [81], [94], [95] What is turned-off Only data array (and not tag array) [29], [80], [96] both data and tag arrays (almost all others) Profiling: offline Offline (or compiler analysis) [41], …”

“…Among techniques using dynamic reconfiguration, some techniques switch cache blocks at the boundary of a fixed, large interval size [13], [20], [23]- [25], [42], [43], [52], [81], [82], [84], [92], [94]; some techniques use variable interval size (time length) [29], [79], [80], some techniques switch cache blocks throughout the execution (for example, before or after cache accesses) [30], [31], [41], [45], [52], [53], [78], [86], [87].…”

“…Based on this granularity, leakage energy saving techniques can be classified as way-level [20], [52], [53], [56], [89]- [93], set-level (or bank-level) [43], [92], hybrid (set and way) level [23], [81], [94], cache block-level [13], [29], [31], [41], [42], [45], [78]- [80], [84], [88], cache sub-block level [86], cache color level [24]- [26] or cache subarray level [82] etc.…”

“…State-destroying techniques (e.g., [44]) do not preserve the state of the turned-off block, but generally save more energy in the low-power states than the state-preserving techniques. Several microarchitecture level techniques utilize state-preserving leakage control (e.g., [19], [31], [39], [42], [45], [52], [53], [79]), while others employ state-destroying leakage control (e.g., [13], [20], [23]- [25], [29], [43], [70], [80]- [86]). Some researchers have proposed techniques which work with either of or both of state-preserving or statedestroying leakage control mechanism [30], [41], [87], [88].…”