Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors

Wang, Xiaorui; Ma, Kai; Wang, Yefu

doi:10.1109/icpp.2010.9

Cited by 13 publications

(5 citation statements)

References 43 publications

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“…(All pipeline stages width=1). As can be seen in Fig.1 results show that although having bigger cache is one of the performance improvement approaches in embedded processors [5,[12][13][14] however by increasing the cache size over a threshold level, performance improvement is saturated and then, decreased. It's because , increasing the cache size, leads to more cache access delays and means that increasing the cache size always is not applicable as an approach to have better performance for embedded processors.…”

Section: A Performance Analysismentioning

confidence: 77%

Cache power and performance tradeoffs for embedded applications

Alipour

Salehi

Moshari

2011

2011 IEEE International Conference on Computer Applications and Industrial Electronics (ICCAIE)

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As embedded applications have became more complex, design of embedded processors has created a research area for low power and yet high performance architectures. Power consumption is as important as performance in battery-powered embedded systems and in future, embedded processors are to process more computationintensive applications with limited power budgets. Therefore, power consumption of theses processors will become more critical. According to the high contribution of memory access power in total power consumption of embedded systems, memory architecture of embedded systems strongly influences the system design objectives. Cache memories are usually used to improve the performance and power consumption by bridging the gap between the speed and power consumption of the main memory and CPU, therefore, the system performance and power consumption is severely related to the average memory access time and power consumption which makes the cache architecture as a major concern in designing embedded processors. Therefore, the embedded system designer requires a comprehensive design space exploration for memory architecture. In this paper we explore the design space of cache in embedded processors to find out the cache sizes which have the optimum performance/power consumption in embedded applications.

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Section: A Performance Analysismentioning

confidence: 77%

Cache power and performance tradeoffs for embedded applications

Alipour

Salehi

Moshari

2011

2011 IEEE International Conference on Computer Applications and Industrial Electronics (ICCAIE)

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“…According to previous work [34], cache leakage power can be modeled as a linear function of active cache size. We adopt the method proposed in [24], [14], [37] to model L2 cache power consumption as:…”

Section: Controller Design For Shared L2 Cachementioning

confidence: 99%

DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance

Wang

2014

IEEE Trans. Comput.

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A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP's cooling, packaging, and power supply capacities. Most existing solutions rely solely on dynamic voltage and frequency scaling (DVFS) to adapt the power consumption of CPU cores, without coordinating with the last-level on-chip (e.g., L2) cache. This paper proposes DPPC, a chip-level power partitioning and control strategy that can dynamically and explicitly partition the chip-level power budget among different CPU cores and the shared last-level cache in a CMP based on the workload characteristics measured online. DPPC features a novel performance-power model and an online model estimator to quantitatively estimate the performance contributed by each core and the cache with their respective local power budgets. DPPC then re-partitions the chip-level power budget among them for optimized CMP performance. The partitioned local power budgets for the CPU cores and cache are precisely enforced by power control algorithms designed rigorously based on feedback control theory. Our extensive experimental results demonstrate that DPPC achieves better CMP performance, within a given power budget, than several state-of-the-art power control solutions for both SPEC CPU2006 benchmarks and multi-threaded SPLASH-2 workloads.

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“…Note that the hardware mechanism to turn o® a portion of LLC is already provided by the existing commercial processor chips 55 and several studies also use the approach of turning o® cache banks to save leakage energy. 56 Here I shows the total number of intervals, and ðS H i ; W H i Þ denotes the actual con¯guration used in an interval i.…”

Section: Pro¯ling Cache Designmentioning

confidence: 99%

EnCache: A DYNAMIC PROFILING-BASED RECONFIGURATION TECHNIQUE FOR IMPROVING CACHE ENERGY EFFICIENCY

Mittal

Zhang

2014

J CIRCUIT SYST COMP

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With each CMOS technology generation, leakage energy consumption has been dramatically increasing and hence, managing leakage power consumption of large last-level caches (LLCs) has become a critical issue in modern processor design. In this paper, we present EnCache, a novel software-based technique which uses dynamic pro¯ling-based cache recon¯guration for saving cache leakage energy. EnCache uses a simple hardware component called pro¯ling cache, which dynamically predicts energy e±ciency of an application for 32 possible cache con¯gurations. Using these estimates, system software recon¯gures the cache to the most energy e±cient con¯guration. EnCache uses dynamic cache recon¯guration and hence, it does not require o®line pro¯ling or tuning the parameter for each application. Furthermore, EnCache optimizes directly for the overall memory subsystem (LLC and main memory) energy e±ciency instead of the LLC energy e±ciency alone. The experiments performed with an Â86-64 simulator and workloads from SPEC2006 suite con¯rm that EnCache provides larger energy saving than a conventional energy saving scheme. For single core and dual-core system con¯gurations, the average savings in memory subsystem energy over a shared baseline con¯guration are 30.0% and 27.3%, respectively

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Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors

Abstract: Limiting the peak power consumption of chip multiprocessors (CMPs)

Cited by 13 publications

References 43 publications

Cache power and performance tradeoffs for embedded applications

Cache power and performance tradeoffs for embedded applications

DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance

EnCache: A DYNAMIC PROFILING-BASED RECONFIGURATION TECHNIQUE FOR IMPROVING CACHE ENERGY EFFICIENCY

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