EnCache: A DYNAMIC PROFILING-BASED RECONFIGURATION TECHNIQUE FOR IMPROVING CACHE ENERGY EFFICIENCY

Abstract

With each CMOS technology generation, leakage energy consumption has been dramatically increasing and hence, managing leakage power consumption of large last-level caches (LLCs) has become a critical issue in modern processor design. In this paper, we present EnCache, a novel software-based technique which uses dynamic pro¯ling-based cache recon¯guration for saving cache leakage energy. EnCache uses a simple hardware component called pro¯ling cache, which dynamically predicts energy e±ciency of an application for 32 possible cache con¯gurations. Using these estimates, system software recon¯gures the cache to the most energy e±cient con¯guration. EnCache uses dynamic cache recon¯guration and hence, it does not require o®line pro¯ling or tuning the parameter for each application. Furthermore, EnCache optimizes directly for the overall memory subsystem (LLC and main memory) energy e±ciency instead of the LLC energy e±ciency alone. The experiments performed with an Â86-64 simulator and workloads from SPEC2006 suite con¯rm that EnCache provides larger energy saving than a conventional energy saving scheme. For single core and dual-core system con¯gurations, the average savings in memory subsystem energy over a shared baseline con¯guration are 30.0% and 27.3%, respectively

A Survey of Cache Bypassing Techniques

“…CBTs can also be helpful for saving cache energy. For example, cache reconfiguration techniques work by turning off portions of cache for applications/phases with low data locality [22][23][24]. Since bypassing reduces the data traffic to cache, it can allow cache reconfiguration techniques to more aggressively turn-off cache for saving even larger amount of energy.…”

Profiling-Assisted Decoupled Access-Execute

“…The profiling can be performed statically or dynamically on one loop-slice or based on sampling to reduce the overhead. As low-overhead profiling was discussed in numerous previous work [21,26,12], this proposal does not attempt to design new profiling methods. For this work, the experiments were conducted using an offline profiling step to annotate critical loads 1 (even for the JIT-ed version) and we leave for future work integration with state-of-the art lowoverhead profiling techniques [12], tailored to identify long latency loads.…”