A Survey Of Techniques for Architecting DRAM Caches

Mittal, Sparsh; Vetter, Jeffrey S.

doi:10.1109/tpds.2015.2461155

Cited by 40 publications

(15 citation statements)

References 51 publications

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“…Going forward, more progress in these areas is definitely required. Further, comparative evaluation of ReRAM-based PIM architectures with PIM architectures based on other memories such as domain wall memory [83], phase change memory [84] and DRAM [85] is also required.…”

Section: Conclusion and Future Outlookmentioning

confidence: 99%

A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

Mittal

2018

MAKE

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127

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As data movement operations and power-budget become key bottlenecks in the design of computing systems, the interest in unconventional approaches such as processing-in-memory (PIM), machine learning (ML), and especially neural network (NN)-based accelerators has grown significantly. Resistive random access memory (ReRAM) is a promising technology for efficiently architecting PIM- and NN-based accelerators due to its capabilities to work as both: High-density/low-energy storage and in-memory computation/search engine. In this paper, we present a survey of techniques for designing ReRAM-based PIM and NN architectures. By classifying the techniques based on key parameters, we underscore their similarities and differences. This paper will be valuable for computer architects, chip designers and researchers in the area of machine learning.

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Section: Conclusion and Future Outlookmentioning

confidence: 99%

A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

Mittal

2018

MAKE

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127

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“…Cache partitioning is only useful when cache size is not large [50]. It is harmful in some extent for the applications exploiting locality [12], however, it is useful for the application which relies on last level cache [52].…”

Section: Cache Partitioningmentioning

confidence: 99%

“…LRU is considered to be the one of the best replacement techniques in case of data eviction, and designers opt the policy in architecture to identify the data need to be replaced. However, studies have discussed [48,49,50] and some researches proved that if LRU policies are not optimized according to competing resources, it can degrade performance [54]. For example, some of LRU based replacement policies do not work with some of cache partitioning techniques which are designed considering full-associative caches [52] and applied to set-associate caches [52].…”

Section: Lru Replacementmentioning

confidence: 99%

On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

Zahid

Khurshid

Memon

2018

ITC

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With the increasing need of computational power the trend towards multicore processors is ubiquitous. The current on-chip architecture comprises multiple cores which usually share last level cache which can be physically distributed on chip. In order to provide system predictability, especially for a real time system where quality of service (QoS) depends on minimum miss rates and low worst case execution time (WCET) for applications running on different cores, efficient cache management techniques are required. Since memory hierarchy and its management is the key of overall system performance and access to off-chip memory for data consumes many clock cycles along with many units of power it is important to restrict the off-chip access and provide the optimum solution for the on-chip access. To increase performance and energy efficiency, various techniques are proposed. This article aims to provide the researchers with the state-of-the-art critical review of the various approaches that focus on data replication and cache partitioning techniques for L3 cache. The existing literature is presented through several classifications based on appropriate design and algorithm. Maintaining energy efficient system is a crucial challenge for multicore processors. We have discussed various techniques which address upscaling performance without compromising on energy efficiency. Lastly, different literature work is discussed where authors evaluate cache and/or various processors for high performance applications such as bioinformatics, image and video processing, IOT applications and applications using DSP processors.

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“…To mitigate these challenges, researchers have explored several alternative low-leakage technologies, such as eDRAM [10,29], die-stacked DRAM [30] and NVM [5,21], etc. While eDRAM has high write-endurance, its main limitation is the requirement of refresh operations to maintain data integrity.…”

Section: Sram Limitations and Emerging Technologiesmentioning

confidence: 99%

A Technique for Improving Lifetime of Non-Volatile Caches Using Write-Minimization

Mittal

Vetter

2016

JLPEA

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While non-volatile memories (NVMs) provide high-density and low-leakage, they also have low write-endurance. This, along with the write-variation introduced by the cache management policies, can lead to very small cache lifetime. In this paper, we propose ENLIVE, a technique for ENhancing the LIfetime of non-Volatile cachEs. Our technique uses a small SRAM (static random access memory) storage, called HotStore. ENLIVE detects frequently written blocks and transfers them to the HotStore so that they can be accessed with smaller latency and energy. This also reduces the number of writes to the NVM cache which improves its lifetime. We present microarchitectural schemes for managing the HotStore. Simulations have been performed using an x86-64 simulator and benchmarks from SPEC2006 suite. We observe that ENLIVE provides higher improvement in lifetime and better performance and energy efficiency than two state-of-the-art techniques for improving NVM cache lifetime. ENLIVE provides 8.47×, 14.67× and 15.79× improvement in lifetime or two, four and eight core systems, respectively. In addition, it works well for a range of system and algorithm parameters and incurs only small overhead.

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A Survey Of Techniques for Architecting DRAM Caches

Cited by 40 publications

References 51 publications

A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

A Survey of ReRAM-Based Architectures for Processing-In-Memory and Neural Networks

On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

A Technique for Improving Lifetime of Non-Volatile Caches Using Write-Minimization

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