DPPC: Dynamic Power Partitioning and Control for Improved Chip Multiprocessor Performance

Abstract

A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP's cooling, packaging, and power supply capacities. Most existing solutions rely solely on dynamic voltage and frequency scaling (DVFS) to adapt the power consumption of CPU cores, without coordinating with the last-level on-chip (e.g., L2) cache. This paper proposes DPPC, a chip-level power partitioning and control strategy that can dynamically and explicitly partition the chip-level power budget among different CPU cores and the shared last-level cache in a CMP based on the workload characteristics measured online. DPPC features a novel performance-power model and an online model estimator to quantitatively estimate the performance contributed by each core and the cache with their respective local power budgets. DPPC then re-partitions the chip-level power budget among them for optimized CMP performance. The partitioned local power budgets for the CPU cores and cache are precisely enforced by power control algorithms designed rigorously based on feedback control theory. Our extensive experimental results demonstrate that DPPC achieves better CMP performance, within a given power budget, than several state-of-the-art power control solutions for both SPEC CPU2006 benchmarks and multi-threaded SPLASH-2 workloads.

Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sources

“…For example, [6] proposed a method where the number of cores that can be powered on is coarsely determined, after which fine-grained frequency adjustment is followed. Most of these approaches are heuristic-based [4]- [6], or linear programming-based [11]. Heuristic-based approaches cannot find the optimal solutions when the number of resources to be controlled is increased or when the applications' behavior becomes complicated.…”

A low cost, high performance dynamic-programming-based adaptive power allocation scheme for many-core architectures in the dark silicon era

“…In the literature, online power budgeting can be achieved by applying various circuit and/or architectural techniques, including frequency/voltage scaling [3], [7], or power gating to control the power consumed by the resources [6].…”

“…The problem of performance optimization under power budget is solved either using some sort of heuristics [3], [4], [6], [7], or formulating it as a linear programming program [7]. Heuristics-based approaches do not generate optimal solutions and their performance can degrade severely with the increase of the number of resources to be controlled.…”

“…Heuristic based approaches, like [3], [4] might fail to find a good solution with low execution cycles, due to the fact that the number of possible combinations of assigning N variables grows exponentially. Linear programming [7] or exhaustive search take unacceptable long time to find the optimal solution.…”

“…end end end end both the number and the frequency of tiles can be adjusted, (2) PEPON [3], where the frequency of each processor and last-level cache bank can be adjusted, and (3) DPPC [7], a linear programming based approach.…”