A power-efficient migration mechanism for D-NUCA caches

Bardine,; Comparetti,; Foglia,; Gabrielli,; Prete,

doi:10.1109/date.2009.5090736

Cited by 12 publications

(11 citation statements)

References 6 publications

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“…D-NUCA can mitigate the large latency associated with frequent remote block access under S-NUCA through gradually migrating the frequently accessed block to the requestor. However, the performance improvements yielded by block migration in D-NUCA could be limited by the ping-pong effect as well as the conflict hit phenomenon [4], [14]. In this work, we propose thread-aware migration policy to eliminate these issues.…”

Section: Background and Related Workmentioning

confidence: 90%

“…Moreover, the on-chip network power is obtained using Orion [23] which is integrated in GEMS framework. We compare the proposed TOM scheme with a baseline D-NUCA [1] substrate and the power-efficient migration scheme (PEM [24] for short). For TOM, the number of critical threads selected by thread categorization is set to 2.…”

Section: A Evaluation Methodologymentioning

confidence: 99%

“…With the help of centralized tags, the conflicts in nearest banks could be reduced. Bardine et al [24] proposed to selectively and dynamically inhibit block migration in D-NUCA to save energy for single-core system. For NUCA in CMP systems, Bechmann and Wood [12] show that block migration in D-NUCA is less effective compared with single core systems.…”

Section: Background and Related Workmentioning

confidence: 99%

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Thread Progress Aware Block Migration for Dynamic NUCA

Ouyang

et al. 2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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Non-Uniform Cache Architecture (NUCA) is a viable solution for large capacity on-chip caches to manage the increasing wire delay. Dynamic NUCA divides the lastlevel cache (LLC) into smaller cache banks connected by on-chip network. D-NUCA yields good performance through migrating blocks within bank sets at runtime to harness data locality. Various works have well explored and studied D-NUCA, including block migration, mapping and searching. However, all of the previous D-NUCA design are threadoblivious. Due to the interference on shared resources, threads often demonstrate unbalanced progress wherein the lagging threads with slow progress are more critical to overall performance. In this paper, we propose a novel D-NUCA design called Thread prOgress aware block Migration (TOM). TOM exploits the dynamic thread criticality information to control block migration. TOM aims at boosting the execution of critical threads through biased block migration. Experimental results show that TOM can effectively reduce the execution time of a set of PARSEC applications with less energy dissipation compared with previous D-NUCA design.

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Section: Background and Related Workmentioning

confidence: 90%

Section: A Evaluation Methodologymentioning

confidence: 99%

Section: Background and Related Workmentioning

confidence: 99%

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Thread Progress Aware Block Migration for Dynamic NUCA

Ouyang

et al. 2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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“…As a consequence, while in the 8p topology both the applications succeed in bringing the blocks in the low latency lines, with the 4+4p topology barnes present an utilization of about 50% of the central lines. This phenomenon is known as conflict hit [23]: a thread accesses a block, and the block migrates in the next bank toward the requestor. However, another thread running on a cpu plugged at the opposite side of the D-NUCA accesses the same block, that consequently migrates back to the previous bank.…”

Section: Influence Of Mapping Topology and Applications Featuresmentioning

confidence: 98%

Analysis of Performance Dependencies in NUCA-Based CMP Systems

Foglia

Panicucci

Prete

et al. 2009

2009 21st International Symposium on Computer Architecture and High Performance Computing

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Improvements in semiconductor nanotechnology have continuously provided a crescent number of faster and smaller per-chip transistors. Consequent classical techniques for boosting performance, such as the increase of clock frequency and the amount of work performed at each clock cycle, can no longer deliver to significant improvement due to energy constrains and wire delay effects. As a consequence, designers interests have shifted toward the implementation of systems with multiple cores per chip (Chip Multiprocessors, CMP). CMP systems typically adopt a large last-level-cache (LLC) shared among all cores, and private L1 caches. As the miss resolution time for private caches depends on the response time of the LLC, which is wire-delay dominated, performance are affected by wire delay. NUCA caches have been proposed for single and multi core systems as a mechanism for such tolerating wire-delay effects on the overall performance. In this paper, we introduce our design for S-NUCA and D-NUCA cache memory systems, and we present an analysis of an 8-cpu CMP system with two levels of cache, in which the L1s are private, while the L2 is a NUCA shared among all cores. We considered two different system topologies (the first with the eight cpus connected to the NUCA at the same side -8p-, the second with half of the cpus on one side and the others at the opposite side -4+4p), and for all the configurations we evaluate the effectiveness of both the static and dynamic policies that have been proposed. Our results show that adopting a D-NUCA scheme with the 8p configuration is the best performing solution among all the considered configurations, and that for the 4+4p configuration the D-NUCA outperforms the S-NUCA in most of the cases. We highlight that performance are tied to both mapping strategy variations (Static and Dynamic) and topology changes. We also observe that bandwidth occupancy depends on both the NUCA policy and topology

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“…In CMP configurations in which processors are placed at different sides of the shared D-NUCA cache, such as our reference system shown in Figure 1, performance improvements due to the migration process can be limited by the conflict hit phenomenon [23]. In CMP systems, such problem is related to the presence of shared blocks that are accessed by threads running on processors placed at opposite sides of the shared cache.…”

Section: Introductionmentioning

confidence: 99%

Re-NUCA: Boosting CMP Performance Through Block Replication

Foglia

Prete

Solinas

et al. 2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Chip Multiprocessor (CMP) systems have become the reference architecture for designing micro-processors, thanks to the improvements in semiconductor nanotechnology that have continuously provided a crescent number of faster and smaller per-chip transistors. The interests for CMPs grew up since classical techniques for boosting performance, e.g. the increase of clock frequency and the amount of work performed at each clock cycle, can no longer deliver to significant improvement due to energy constrains and wire delay effects. CMP systems generally adopt a large last-level-cache (LLC) (typically, L2 or L3) shared among all cores, and private L1 caches. As the miss resolution time for private caches depends on the response time of the LLC, which is wire-delay dominated, performance are affected by wire delay. NUCA caches have been proposed for single and multi core systems as a mechanism for tolerating wire-delay effects on the overall performance. In this paper, we introduce a novel NUCA architecture, called Re-NUCA, specifically suited for (but not limited to) CMPs in which cores are placed at different sides of the shared cache. The idea is to allow shared blocks to be replicated inside the shared cache, in order to avoid the limitations to performance improvements that arise in classical D-NUCA caches due to the conflict hit problem. Our results show that Re-NUCA outperforms D-NUCA of more then 5% on average, but for those applications that strongly suffer from the conflict hit problem we observe performance improvements up to 15%.

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A power-efficient migration mechanism for D-NUCA caches

Cited by 12 publications

References 6 publications

Thread Progress Aware Block Migration for Dynamic NUCA

Thread Progress Aware Block Migration for Dynamic NUCA

Analysis of Performance Dependencies in NUCA-Based CMP Systems

Re-NUCA: Boosting CMP Performance Through Block Replication

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