Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits

Kim, Keunwoo; Das, Koushik K.; Joshi, Rajiv V.; Chuang, Ching-Te

doi:10.1109/ted.2005.846317

Cited by 36 publications

(27 citation statements)

References 18 publications

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“…In this study, both NMOS and PMOS transistors are designed to have I OFF in the proximity of 1 pA as mentioned previously. This value is significantly smaller than the OFF currents found in double-gated SOI transistors in earlier modeling studies [3][4][5] and several orders of magnitude smaller than the value predicted by Sery [6]. Figure 2.2 shows I OFF as a function of I ON for wire radius between 1 nm and 10 nm and effective channel lengths between 5 nm and 37 nm for transistors producing 1 pA or smaller OFF currents.…”

Section: The Off Current Requirement For the Designmentioning

confidence: 66%

“…The amount of DIBL is 114 mV/V for the NMOS and 69 mV/V for the PMOS transistors with 4 nm radius and 7 nm effective channel length. Figure 2.4 shows these values along with previously published data for comparison purposes [3,7,9,11,13,14].…”

Section: Characteristics Of the Selected Nmos And Pmos Transistorsmentioning

confidence: 81%

“…The gate oxide tunneling mechanisms and hot carrier injection are also ignored because these mechanisms largely depend on oxide growth and composition. Kim et al [3] also pointed out that gate current constituted only a small percentage of the total OFF current for double-gated SOI devices with 1.5 nm gate oxide thickness.…”

Section: Physical Models Used In Device Simulationsmentioning

confidence: 99%

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Single Work Function Silicon Nanowire MOS Transistors

Bindal

Hamedi-Hagh

2016

Silicon Nanowire Transistors

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In the first chapter of this book, SNTs with dual work function gates were designed and their device characteristics were examined. Later in the same chapter, basic digital CMOS gates were built; their circuit performance, power dissipation, and layout characteristics were analyzed; basic SNT processing steps were shown. A dual work function CMOS technology requires the use of different metals in NMOS and PMOS transistor gates. Finding the appropriate metals that match exactly to the work function values found in this study may often be a difficult enterprise as it may require alloys for gate material or incompatible metals with the SNT processing.One way to reduce the set of problems associated with dual metals is to use a single metal gate. Therefore, this chapter is dedicated to design NMOS and PMOS transistors with a single work function metal gate, and furthermore use these transistors in designing CMOS circuits.As in Chapter 1, this chapter will also introduce the design criteria for SNTs that use a single metal gate, show the design flow to select optimum device dimensions for both NMOS and PMOS transistors, and analyze speed, power dissipation and layout area characteristics of various CMOS logic gates and mega cells that use these devices.The design criteria for the single work function NMOS and PMOS SNTs are very similar to what has been applied to the dual work function SNTs.1. NMOS and PMOS transistors need to have at least 300 mV threshold voltage for 1 V CMOS circuit operation 2. The static OFF current has to be under 1 pA in either NMOS or PMOS transistor

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Section: The Off Current Requirement For the Designmentioning

confidence: 66%

Section: Characteristics Of the Selected Nmos And Pmos Transistorsmentioning

confidence: 81%

Section: Physical Models Used In Device Simulationsmentioning

confidence: 99%

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Single Work Function Silicon Nanowire MOS Transistors

Bindal

Hamedi-Hagh

2016

Silicon Nanowire Transistors

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“…The potential at the top nsensitive to the local electron charge, and is solely determined by the applied voltage biases found that C G < C Q when V GS > 0.28V so the QCL is not achieved at the the SiO 2 layer [7][8][9][10][11][12]. …”

Section: International Journal Of Advanced Engineering Research and Smentioning

confidence: 99%

Analysis of Phenomenon at Quantum Capacitance Limit of SNWFET using FETToy

Mishra¹,

Shukla²,

Tripathi³

et al. 2016

IJAERS

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“…Double Gate FinFET has two gates, one is front gate and other is back gate, it provides flexibility in design with low power and delay. Due to its low leakage structure, the current strength ratio also improves [8][9][10][11][12]. FinFET top and crosssectional view is demonstrated in fig.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of FinFET based Carry save Adder Cell with Predictive Technology Models

Baghel¹,

Kaur²,

Singh³

2015

IJCA

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As scaling of conventional metal-oxide-semiconductor field effect transistor is approaching its fundamental and technological limits, alternate device solutions are being developed. FinFET is rapidly replacing conventional CMOS transistors as it offer lot of improvements in power consumption, propagation delay and propagation delay product (PDP). This paper presents design & simulation of a double gate FinFET based ultra low power 2-bit Carry Save Adder (CSA) cell. A comprehensive comparison of FinFET and CMOS based 2-bit carry save adder has been performed. The CMOS & FinFET based 2-bit carry save adder circuits are evaluated at 32nm & 45nm nanoscale technology nodes using Predictive Technology Models (PTM). At 45nm technology node, the FinFET based carry save adder results shows average power consumption reduction of 39.75%; propagation delay reduction of 92.50% and a propagation delay product (PDP) improvement of 94.42% as compared to CMOS counterparts. The FinFET based carry save adder results shows average power consumption reduction of 42.19%; propagation delay reduction of 86.86% and a propagation delay product (PDP) improvement of 92.22% as compared to CMOS based carry save adder at 32nm technology node.

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Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits

Cited by 36 publications

References 18 publications

Single Work Function Silicon Nanowire MOS Transistors

Single Work Function Silicon Nanowire MOS Transistors

Analysis of Phenomenon at Quantum Capacitance Limit of SNWFET using FETToy

Performance Analysis of FinFET based Carry save Adder Cell with Predictive Technology Models

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