This paper presents the design of high speed multiplier and squaring architectures based upon ancient Indian Vedic mathematics sutras. In existing Vedic multiplier architectures, the partial product terms are computed in parallel and then added at the end to get the final result. In this work, all the partial products are adjusted using concatenation operation and are added using single carry save adder instead of two adders at different stages. The high speed Vedic multiplier architecture is then used in the squaring modules. The reduced number of computations in multiplication due to adjusting using concatenation operation and one carry save adder only, the designed multiplier offers significant improvement in speed. The designed architectures are realized using Xilinx Spartan-3E FPGA. The comparison shows the 28.72% and 38.59% reduction in propagation delay for the designed 32-bit multiplier as compared to the existing multiplier designs.
Emerging nanoscale computing structure quantum-dot cellular automata (QCA) is evolving as a possible replacement for complementary metal-oxide-semiconductor technology in near future. Being a new technology, it is prone to various types of fabrication-related faults and process variations. So, QCA-based circuits are prone to errors, and therefore pose significant reliability-related issues. Hence, there is an emerging need to design fault-tolerant QCA-based circuits to mitigate the reliability issues. This study first presents QCA-based new designs of 2-input Exclusive-OR gate and 1 bit full adder using conventional design approach without redundant QCA cells. Then, the fault tolerance has been implemented in these designs by introducing redundant QCA cells. The proposed circuits exhibit significant improvements in fault-tolerant capability against cell omission, misalignment, displacement, and extra cell deposition defects. The proposed fault-tolerant designs have been compared with existing designs in terms of generalised design metrics of QCA circuits. Energy dissipation results have been computed for the proposed fault-tolerant circuits using accurate QCAPro power estimator tool. Influence of temperature variations on the polarisation of the proposed fault-tolerant circuits has also been investigated. The functionality of the proposed circuits has been verified with QCADesigner version 2.0.3 tool.
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