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This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied until a common body geometry is determined for both nMOS and pMOS transistors to limit OFF currents under 1 pA while producing highest ON currents. DC characteristics of the optimum and -channel transistors such as threshold voltage roll-off, DIBL and subthreshold slope are measured; simple CMOS gates including an inverter, 2-and 3-input NAND, NOR, and XOR gates, and full adder are built to measure the transient performance, power dissipation and layout area. Postlayout simulation results indicate that the worst case delay for a full adder circuit is 8.5 ps at no load and increases by 0.15 ps/aF; worst case power dissipation of the same circuit is 23.6 nW at no load and increases by 4.04 nW/aF at 1 GHz. The full adder layout area occupies approximately 0.11 m 2 .Index Terms-Low-power very large scale integration (VLSI), metal-gate transistors, nanowire transistors, vertical silicon transistors.

This paper presents the design of an inductor and an antenna for a portable device with GPS and FM capabilities. The inductor is designed to operate at the lower frequency FM band as part of a matching network and the antenna is designed to operate at the higher frequency GPS L1 band. The FR4 PCB used has a thickness of 1.6 mm with a dielectric constant of 3.8 and has two metallization layers. The inductor is designed with 1.5 mm trace width, 3.5 turns, and has a dimension of 14.5 mm × 14.5 mm. It has an inductance of 95 nH, a resistance of 2.9 Ω, a self-resonance frequency of 500 MHz, and a maximum Q of 51 from 100 MHz to 200 MHz (FM band). The antenna has a dimension of 49 mm × 36 mm and is designed to operate at 1.5754 GHz L1 band. It also has a return loss of −36 dB and a measured bandwidth of 250 MHz.

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A novel non-coherent, low-power, area-efficient binary phase-shift keying demodulator for wireless implantable biomedical microsystems is proposed. The received data and synchronized clock signal are detected using a delayed digitized format of the input signal. The proposed technique does not require any kind of oscillator circuit, and due to the synchronization of all circuit signals, the proposed demodulator can work in a wide range of biomedical data telemetry common frequencies in different process/temperature corners. The presented circuit has been designed and post-layout-simulated in a standard 0.18 μm CMOS technology and occupies 17 × 27 μm2 of active area. Post-layout simulation results indicate that with a 1.8 V power supply, power consumption of the designed circuit is 8.5 μW at a data rate of 20 Mbps. The presented demodulation scheme was also implemented on a proof-of-concept circuit board for verifying its functionality.

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