Extra Bit Generation for High-Speed Time-Based Flash ADCs in 65nm CMOS

Analysis of strong-arm comparator with auxiliary pair for offset calibration

“…9(a) shows the input-referred noise simulation result when we keep W/L ratio of the transistors in the circuit constant and scale all transistors simultaneously in the same proportion, which is defined as n. Since increasing sizes of transistors give larger parasitic capacitance considered as load capacitor pairs while keeping the current through the comparator, it leads to larger T s and T p according to (3) and (4). Thus, the input-referred thermal noise voltage decreases with the trend of 1= ffiffi ffi n p according to (9). Fig.…”

“…With the introduction of the auxiliary pair, by replacing the noise current PSD and time windows in (9) with the values for the Strong-Arm with the auxiliary pair, the input-referred noise voltage is given by…”

“…When we change the length L M7;8 and fix the width W M7;8 , b 7;8 changes, but the parasitic capacitance from the auxiliary pair does not increase, which means g is fixed. Regardless of the ratio of C C to C L , the input noise increases by r ¼ 1 þ a times according to (9). When we fix the length L M7;8 and change the width W M7;8 , on the other hand, b 7;8 increases while the additional parasitic capacitance from the auxiliary pair also increases.…”

“…These large capacitors will significantly reduce the comparator operating speed. The unbalanced clock is introduced to compensate for the input-referred offset voltage caused by the process error by adjusting the clock signal [7][8][9]. Several clock signals (i.e., three clocks in [7,8]) greatly increase the complexity of chip design.…”

International Journal of Electronics and Telecommunications

“…Mehdi Nasrollahpour [10] proposed the open-loop comparator circuit which comprises analog input and reference input. This comparator consists of the differential amplifier, input, and output phase.…”