Leakage-aware redundancy for reliable sub-threshold memories

Kim, Seokjoong; Guthaus, Matthew R.

doi:10.1145/2024724.2024826

Cited by 4 publications

(3 citation statements)

References 26 publications

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“…Therefore, the power consumption is reduced by only using the high supply voltage when necessary. We calculate the V high supply voltages by analyzing the memory access delay constraint of a read operation and calculate the DRV using Monte-carlo SNM analysis [9]. The write operation is not directly considered, because the read operation has less noise margin and is more critical than the write operation [26].…”

Section: Seu-aware Low-power Memory Arraymentioning

confidence: 99%

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

Kim

Guthaus

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Electric devices should be resilient because reliability issues are increasingly problematic as technology scales down and the supply voltage is lowered. Specifically, the Soft-Error Rate (SER) increases due to the reduced feature size and the reduced charge. This paper describes an adaptive method to lower memory power using a dual V dd in a column-based V dd memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods.

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Section: Seu-aware Low-power Memory Arraymentioning

confidence: 99%

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

Kim

Guthaus

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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“…There fore, the power consumption is reduced by only using the high supply voltage when necessary. We calculate the Vhigh supply voltages by analyzing the memory access delay constraints of a read operation and calculate the D RV using Monte-carlo based SNM analysis framework [7]. Write operation is not directly considered, because the read operation is more critical than the write operation that needs less noise margin [24].…”

Section: A Adaptive Supply Voltage Strategymentioning

confidence: 99%

Dynamic voltage scaling for SEU-tolerance in low-power memories

Guthaus¹

2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

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Reliability issues are iucreasiugly problematic as techuology scales dowu aud the su pp ly voltage is lowered.Specifically, the Soft-Error Rate (SER) iucreases due to the reduced feature size aud the reduced charge. This p a p er describes au ada p tive method to lower memory p ower usiug a dual Vdd iu a columu-based Vdd memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory p ower by about 40% and increase the error immunity of the memory without the significant power overhead as in p revious methods.

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“…This has been accompanied by successful low-power design techniques such as supply voltage scaling [13], dynamic voltage and frequency scaling [10], interconnect optimization [11], error tolerant voltage optimization [18], pipe-lining [3], leakage-aware memory redundancy [17], and gating of func tional blocks [12], which have ensured thermal density, power density and yield do not reach detrimental levels. While some of these techniques yield significant improvement in specific applications, overall, the maximal power savings are obtained by way of supply voltage scaling.…”

Section: Introductionmentioning

confidence: 99%

A single-VDD ultra-low energy sub-threshold FPGA

Sankaranarayanan¹,

Guthaus²

2012

2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)

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Sub-threshold operation in CMOS has in recent years become an accepted ultra-low power solution. However, many low-volume applications cannot afford to produce custom silicon. An FPGA, which delivers the flexibility of programming and yet consumes ultra-low power by way of sub-threshold operation, can fill this gap. In this work we propose a single VDD sub-threshold FPGA, map a benchmark circuit application to it and analyze the resulting fabric from various standpoints. The constituent blocks functionally work down to HOmV and the ISCAS benchmark mapped onto the fabric has a minimum energy point around 200m V while consuming 8pJ/operation. These results serve as the foundation to further investigate energy efficiency in the context of sub-threshold operation and identify limits of scale, impact of design styles and achievable performance.

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Leakage-aware redundancy for reliable sub-threshold memories

Cited by 4 publications

References 26 publications

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

Dynamic voltage scaling for SEU-tolerance in low-power memories

A single-VDD ultra-low energy sub-threshold FPGA

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