SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

Abstract

Abstract. Electric devices should be resilient because reliability issues are increasingly problematic as technology scales down and the supply voltage is lowered. Specifically, the Soft-Error Rate (SER) increases due to the reduced feature size and the reduced charge. This paper describes an adaptive method to lower memory power using a dual V dd in a column-based V dd memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods.

DPCS

“…They are also similar in that they either reduce the effective cache capacity by disabling faulty regions as VDD is reduced (e.g., FFT-Cache [BanaiyanMofrad et al 2011]), or boost VDD in "weak" regions as necessary to maintain capacity (e.g., Sasan et al [2012]). Han et al [2013] and Kim and Guthaus [2013] both utilize multiple memory supply voltages. Ghasemi et al [2011] proposed a lastlevel cache with heterogeneous cell sizes for more graceful voltage/capacity trade-offs.…”