A single-VDD ultra-low energy sub-threshold FPGA

Abstract

Sub-threshold operation in CMOS has in recent years become an accepted ultra-low power solution. However, many low-volume applications cannot afford to produce custom silicon. An FPGA, which delivers the flexibility of programming and yet consumes ultra-low power by way of sub-threshold operation, can fill this gap. In this work we propose a single VDD sub-threshold FPGA, map a benchmark circuit application to it and analyze the resulting fabric from various standpoints. The constituent blocks functionally work down to HOmV and the ISCAS benchmark mapped onto the fabric has a minimum energy point around 200m V while consuming 8pJ/operation. These results serve as the foundation to further investigate energy efficiency in the context of sub-threshold operation and identify limits of scale, impact of design styles and achievable performance.