Dynamic voltage scaling for SEU-tolerance in low-power memories

Abstract

Reliability issues are iucreasiugly problematic as techuology scales dowu aud the su pp ly voltage is lowered.Specifically, the Soft-Error Rate (SER) iucreases due to the reduced feature size aud the reduced charge. This p a p er describes au ada p tive method to lower memory p ower usiug a dual Vdd iu a columu-based Vdd memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory p ower by about 40% and increase the error immunity of the memory without the significant power overhead as in p revious methods.