Layered T comparator design using quantum-dot cellular automata

Roy, Santanu; Mukherjee, Chiradeep; Panda, Saradindu; Mukhopadhyay, Asish K.; Maji, Bansibadan

doi:10.1109/devic.2017.8073913

Cited by 16 publications

(8 citation statements)

References 14 publications

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“…The achieved reduction in the efficient complexity (EC) value has reached up to 26% with respect to that of [26]. In addition, as compared to the first proposed structure (Design A), the area occupied of the design presented in [25] is smaller. However, this reduction in area was due to the increased number of QCA layers (i.e., multilayers) and not primarily from the logic design.…”

Section: Resultsmentioning

confidence: 96%

“…In their study, three Feynman QCA gates were used to achieve the intended outputs (A>B, A<B and A=B). Roy et al [25] have proposed two implementations of 1-bit comparator using the layered-T AND and OR gates. The number of cells requirement of their proposed designs was 40 and 37 QCA cells with an occupational area of 0.032 μm 2 and 0.028 μm 2 , respectively.…”

Section: Introductionmentioning

confidence: 99%

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Design and analysis of single layer quantum dot-cellular automata based 1- bit comparators

Altarawneh

Al-Tarawneh

2022

TELKOMNIKA

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Section: Resultsmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

Design and analysis of single layer quantum dot-cellular automata based 1- bit comparators

Altarawneh

Al-Tarawneh

2022

TELKOMNIKA

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“…24 Crossovers are required in the design. Two comparator circuits have been proposed in 25 using 40 and 37 QCA cells. The idea for these comparator circuits is layered T AND and OR gates.…”

Section: Previous Related Workmentioning

confidence: 99%

Optimal design for digital comparator using QCA nanotechnology with energy estimation

Sharma

2020

Int J Numerical Modelling

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Quantum‐dot cellular automata (QCA) is a transistor‐less technology to implement the nanoscale circuit designs. QCA circuits are fast, highly dense and dissipate less energy as compared to widely used complementary metal oxide semiconductor (CMOS) technology. In this paper, a novel structure for digital comparator using QCA nanotechnology is proposed. Digital comparator is a basic and important module in central processing unit which compares two binary numbers. The proposed digital comparator is optimal, single layered with 0.50 clock latency and containing only 26 QCA cells. The proposed digital comparator is compared for the different performance metrics with the existing digital comparators. The calculations for energy dissipation are provided using QCA Designer‐E and QCA Pro tools. The proposed coplanar digital comparator is designed with minimum QCA cells which reduces the total cell area, total covered area and cost. Total cell area, total covered area and cost for the proposed digital comparator are 0.008 μm2, 0.023 μm2 and 0.006 respectively. Results show that energy dissipation for the proposed design is very less therefore, proposed digital comparator is energy efficient.

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“…The designs proposed in [7], [8], [10], [13], [16]- [18] can compare just 1-bit inputs. Some of them are able to simply establish if the inputs a and b are equal [7], whereas others can establish if a < b or a > b [10].…”

Section: Introductionmentioning

confidence: 99%

Multibit Full Comparator Logic in Quantum-Dot Cellular Automata

Perri

Spagnolo

Frustaci

et al. 2022

IEEE Trans. Circuits Syst. II

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In the last few years, binary comparators have received a great deal of attention as parts of complex computational data-paths. However, while several multi-bit architectures have been demonstrated using conventional CMOS technologies, few examples of n-bit comparators, with n higher than 4, can be found in literature for designs based on emerging nanotechnologies, such as the Quantum Dot Cellular Automata, the Nano Magnetic Logic, and many others. This brief proposes a novel approach to design efficient multi-bit binary comparators using the Quantum Dot Cellular Automata nanotechnology. The approach here presented allows improving state-of-the-art competitors in terms of computational complexity and average energy consumption. As an example, in comparison with its direct counterparts, the 32-bit comparator designed as proposed here saves up to 26%, 23% and 11% of the occupied area, the used basic cells and the average energy consumption, respectively. When implemented using the Nano Magnetic Logic, the 4-bit version of the novel comparator uses 1183 magnets and 38 clock phases.

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Layered T comparator design using quantum-dot cellular automata

Cited by 16 publications

References 14 publications

Design and analysis of single layer quantum dot-cellular automata based 1- bit comparators

Design and analysis of single layer quantum dot-cellular automata based 1- bit comparators

Optimal design for digital comparator using QCA nanotechnology with energy estimation

Multibit Full Comparator Logic in Quantum-Dot Cellular Automata

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