Design and analysis of single layer quantum dot-cellular  automata based 1- bit comparators

Altarawneh, Ziyad; Al-Tarawneh, Mutaz

doi:10.12928/telkomnika.v20i1.18434

Cited by 2 publications

(1 citation statement)

References 30 publications

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“…Bharathi et al [20] presented energy-efficient D flip-flop, half adder, and full adder circuit designs and implemented them using sub-threshold adiabatic logic with two-phase clocking. Now days, many researches has been reported on the design of adders [20]- [24], subtractors [25], comparators [26]- [28], memory [29] and some other combinational and sequential circuits. The schematic and layout design of the presented circuit is unreported in the literature as of yet.…”

Section: Introductionmentioning

confidence: 99%

D flip-flop design by adiabatic technique for low power applications

Sanadhya

Sharma²

2022

IJEECS

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Indigital circuits, energy reduction is the most important parameter in the design of handy and battery-operated devices. Flip- flop is an important component in any digital system. By improving the performance of flip-flop, complete system performance is better. This paper addresses the design of D flip-flop using direct current diode-based positive feedback adiabatic logic (DC-DB PFAL) at various frequencies at 45nm technology node. Further, the layout for the proposed design is also presented. The performance analysis is carried out for delay, power dissipation, power delay product and transistor count. Circuit simulation is done by using cadence virtuoso tool at 10 MHz and 100 MHz frequencies. The results show an improvement in power dissipation of 18% with less transistors count compared to exiting designs in the literature.

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