Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture

Wang, Po-Han; Li, Cheng‐Hsuan; Yang, Chia-Lin

doi:10.1145/2897937.2898036

Cited by 19 publications

(7 citation statements)

References 19 publications

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“…Therefore, the LLC design is a very important issue in multi-core systems. Wang et al [218] have proposed a latency sensitivity-based cache partitioning (LSP) framework. The LSP framework, evaluates a latencysensitivity metric at runtime to adapt the cache partitioning.…”

Section: ) Multi-core Optimizationmentioning

confidence: 99%

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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In order to facilitate flexible network service virtualization and migration, network functions (NFs) are increasingly executed by software modules as so-called "softwarized NFs" on General-Purpose Computing (GPC) platforms and infrastructures. GPC platforms are not specifically designed to efficiently execute NFs with their typically intense Input/Output (I/O) demands. Recently, numerous hardwarebased accelerations have been developed to augment GPC platforms and infrastructures, e.g., the central processing unit (CPU) and memory, to efficiently execute NFs. This article comprehensively surveys hardware-accelerated platforms and infrastructures for executing softwarized NFs. This survey covers both commercial products, which we consider to be enabling technologies, as well as relevant research studies. We have organized the survey into the main categories of enabling technologies and research studies on hardware accelerations for the CPU, the memory, and the interconnects (e.g., between CPU and memory), as well as custom and dedicated hardware accelerators (that are embedded on the platforms); furthermore, we survey hardware-accelerated infrastructures that connect GPC platforms to networks (e.g., smart network interface cards). We find that the CPU hardware accelerations have mainly focused on extended instruction sets and CPU clock adjustments, as well as cache coherency. Hardware accelerated interconnects have been developed for on-chip and chip-to-chip connections. Our comprehensive up-to-date survey identifies the main trade-offs and limitations of the existing hardware-accelerated platforms and infrastructures for NFs and outlines directions for future research.

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Section: ) Multi-core Optimizationmentioning

confidence: 99%

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

2020

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“…Further, the single-tier virtual queuing memory controller [5] was proposed to overcome the limitation of two-tier schedulers in QoS-aware scheduling. Besides memory scheduling, QoSaware cache management [7] and on-chip network design [6] have also been well-explored in recent years. Nonetheless, these work cannot guarantee end-to-end QoS because they only deal with certain parts of the memory system.…”

Section: Related Workmentioning

confidence: 99%

“…Moreover, as latency-sensitive cores such as the DSP share memory with other cores, they can be easily overwhelmed by real-time cores consuming high bandwidth. QoS-aware management for specific types of memory resources has been well-studied by previous work [3,4,5,6,7]. In [3], a QoS-aware scheduling policy was proposed for CPU-GPU systems.…”

Section: Introductionmentioning

confidence: 99%

SARA: Self-Aware Resource Allocation for Heterogeneous MPSoCs

Yang¹,

Alavoine²,

Lin³

2018

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

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“…QoS-aware management for specific types of memory resources has been well studied by previous work [1,4,9,22,25]. In Reference [9], a QoS-aware scheduling policy was proposed for CPU-GPU systems.…”

Section: Introductionmentioning

confidence: 99%

“…With ineffective memory scheduling, a real-time core (e.g., the display) may not achieve the target real-time performance due to inadequate memory bandwidth. Moreover, as latency-sensitive cores such as the DSP share memory with other cores, they can be easily overwhelmed by real-time cores consuming high bandwidth.QoS-aware management for specific types of memory resources has been well studied by previous work [1,4,9,22,25]. In Reference [9], a QoS-aware scheduling policy was proposed for CPU-GPU systems.…”

mentioning

confidence: 99%

A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets

Song

Alavoine

Lin

2019

ACM Trans. Archit. Code Optim.

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In modern heterogeneous MPSoCs, the management of shared memory resources is crucial in delivering end-to-end QoS. Previous frameworks have either focused on singular QoS targets or the allocation of partitionable resources among CPU applications at relatively slow timescales. However, heterogeneous MPSoCs typically require instant response from the memory system where most resources cannot be partitioned. Moreover, the health of different cores in a heterogeneous MPSoC is often measured by diverse performance objectives. In this work, we propose the Self-Aware Resource Allocation framework for heterogeneous MP-SoCs. Priority-based adaptation allows cores to use different target performance and self-monitor their own intrinsic health. In response, the system allocates non-partitionable resources based on priorities. The proposed framework meets a diverse range of QoS demands from heterogeneous cores. Moreover, we present a runtime scheme to configure priority-based adaptation so that distinct sensitivities of heterogeneous QoS targets with respect to memory allocation can be accommodated. In addition, the priority of best-effort cores can also be regulated. This article is an extension of a conference paper: "SARA: Self-Aware Resource Allocation for Heterogeneous MPSoCs," published in DAC'18 (Song et al.). In particular, we extend our work in the following ways: -We add a new section to discuss the challenges of priority-based adaptation in the SARA framework. To deal with the challenges, we introduce a two-stage runtime configuration solution, including distributed self-configuration and global regulation, to accommodate best-effort cores and real-time cores that are particularly sensitive to memory allocation updates.-We expand the evaluation section to include more details on our simulation platform. We also present evaluation results on the runtime configuration scheme for the SARA framework.-In addition, a more comprehensive review of related work is provided in this paper to summarize prior efforts on memory scheduling and management.16:2 Y. Song et al. INTRODUCTIONModern heterogeneous MPSoCs [15,17] have been widely deployed in mobile devices thanks to their energy efficiency. These MPSoCs typically integrate a diverse collection of cores. Figure 1 depicts an example of a heterogeneous MPSoC. Besides general-purpose cores like the CPU for running applications, most heterogeneous cores are dedicated to certain functions, such as the GPU, the DSP, and the display. These cores have diverse notions of Quality-of-Service (QoS). For example, the GPU measures target real-time performance in terms of frame rate, the DSP demands the memory latency to remain below a certain limit, and the display requires sufficient bandwidth to refresh frames at a constant rate.To save cost and energy, heterogeneous cores commonly share resources, among which the sharing of the memory system including the network-on-chip (NoC) and the memory controller (MC) are the most challenging, because memory performance often has a direct and...

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Latency sensitivity-based cache partitioning for heterogeneous multi-core architecture

Cited by 19 publications

References 19 publications

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

Hardware-Accelerated Platforms and Infrastructures for Network Functions: A Survey of Enabling Technologies and Research Studies

SARA: Self-Aware Resource Allocation for Heterogeneous MPSoCs

A Self-aware Resource Management Framework for Heterogeneous Multicore SoCs with Diverse QoS Targets

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