Latch-up in 65nm CMOS technology: a scaling perspective

Abstract

TECHNOLOGIES INVESTIGATEDIn this study, through a detailed analysis of the last four CMOS technology nodes targeting similar applications, the intrinsic latch-up process sensitivity will be investigated in an attempt to assess in which measure latch-up will continue to be a major reliability concern for future CMOS technologies. [Keywor-dy: Latch-up, CMOS for low-power applications, CMOS Scaling, High current behavior] Latch-up (LU) in CMOS technologies is a well-established 0-7803-8803-8/05/~20.

Evidence for Lateral Angle Effect on Single-Event Latchup in 65 nm SRAMs

“…The simulated temperature at which the devices go from latchup-immune to latchup-susceptible matches the experimental data provided for electrical latchup shown by Boselli [26] to within C. Both of these publications predict onset of latchup susceptibility at 340 K, or 67 C. These simulations are based on a single temperature throughout the device. While the simulation/experimental holding voltage in Fig.…”

“…It is common practice to pack devices more tightly in regularly repeating memory arrays than allowed in logic-circuitry design. In addition, the well and substrate resistances seen by sources in the SRAMs are much higher than those seen in the test devices in [15], [26], as those devices were 20 m wide. Given the 30% reduction in the base length of the parasitic bipolar transistors in the feedback path and a more favorable biasing condition with more than a 10 increase in resistance, the most sensitive devices in the SRAM arrays are vulnerable at room temperature.…”

“…From TCAD simulations in [15] and electrical characterization techniques in [26], both using the same 65 nm technology as in this experiment, it would be expected that no latchup would be observed at room temperature. Fig.…”

Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

“…Figure 1 (a) demonstrates the cross section of a DW internal latchup test structure. It can be seen it consists of the NPN and PNP parasitic bipolar transistors [8]. The horizontal and vertical well resistances which depend on the tap spacing and diffusion areas respectively have been drawn in the same figure.…”

Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula>/Metal Gate CMOS Process

“…The silicon-controlled rectifier (SCR) device has been reported to be useful for ESD protection due to its high ESD robustness, small device size, and excellent clamping capabilities (low holding voltage and small turn-ON resistance) [8]- [10]. Besides, the SCR device can be safely used without latchup danger in advanced CMOS technologies with low supply voltage [11]. The ESD protection design for I/O cells with embedded SCR [12] and the high-voltage output arrays with embedded SCR [13] have been reported.…”