Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-&lt;inline-formula&gt; 
                     &lt;tex-math notation="LaTeX"&gt;$k$ &lt;/tex-math&gt;
                  &lt;/inline-formula&gt;/Metal Gate CMOS Process

Lin, Chun Yu; Chang, Po Hsiang; Chang, Rong-Kun

doi:10.1109/ted.2015.2396946

Cited by 15 publications

(1 citation statement)

References 10 publications

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“…Therefore, an attempt was made to design a protection element that would increase the breakdown voltage and reduce the electric field value. Electrostatic discharge (ESD) [1][2][3][4][5][6][7] can occur because of excessive transient currents, which can be caused by the switching on and off of a power supply, the incomplete grounding of a machine, or human contact with an integrated circuit (IC) through human grounding (i.e., the Human Body Model). Notably, ESD can also irreversibly damage an IC.…”

Section: Introductionmentioning

confidence: 99%

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Mai

Chen

et al. 2023

Electronics

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This study used a TSMC 0.18 µm 50 V process to build a high-voltage n-LDMOS structure. In the reference device, the number of floating poly (poly-2) turns was 7, and the width and spacing of each turn was 1 µm. The experiment was realized in three steps, i.e., fixing the number of laps by occupying the width of the structure, adjusting the width of each turn, and adjusting the distance between turns. The first step was fixed to occupy the width of the structure chart to adjust the number of turns. The number of turns increased from 7 to 9 and then decreased to 5 and 3 turns. The reduction in the number of turns resulted in a greater reduction in maximum electric field and an increase in breakdown voltage. A comparison of the 3-turn set with the reference set showed a 42% reduction in maximum electric field, from 4.17 × 103 to 2.46 × 103 (V/cm), and an increase in breakdown voltage (VBK) from 30.2 V to 35.84 V. The second step was to adjust the width of each turn from 1 to 1.4, 1.2, 0.8, and 0.6 µm. This increase in width reduced the maximum electric field, resulting in a greater increase in VBK. When the width was increased to 1.4 µm, the maximum field decreased from 1.95 × 103 V/cm to 1.4 × 103 V/cm and the VBK increased from 30.2 V to 85.6 V, an increase of 183%. The third step was to adjust the per-turn spacing of the reference group from 1 to 1.4, 1.2, 0.8, and 0.6 µm. When the spacing was reduced to 0.6 µm, the maximum electric field decreased by 33% from 1.95 × 103 to 1.32 × 103 V/cm and the VBK increased by 345% from 30.2 to 134.4 V.

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Section: Introductionmentioning

confidence: 99%

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Mai

Chen

et al. 2023

Electronics

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Characteristic parameter model and circuit‐level simulation of gate‐controlled dual direction SCR for on‐chip ESD protection

Liu,

Wang,

Yang

et al. 2024

Circuit Theory & Apps

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SummaryDual‐directional SCR (DDSCR) with bidirectional discharge paths and high robustness is widely employed for electrostatic discharge (ESD) protection in integrated circuits. However, the design and simulation of on‐chip ESD protection circuits for dual‐directional paths remain challenging due to a lack of relevant device models. This paper designs a Gate‐Controlled Dual‐Direction SCR (GDDSCR) for providing electrostatic discharge (ESD) protection in industry‐level temperature sensors. Furthermore, a new behavioral model is developed based on the GDDSCR for simulating ESD protection circuits along both forward and reverse paths. Experimental results demonstrate that the GDDSCR behavioral model accurately reproduces the IV characteristics observed in bidirectional transmission line pulse (TLP) tests. In addition, the equivalent circuit based on human body model (HBM) is used for transient simulation, and the accuracy of the model is verified by relevant HBM experiments. The proposed model allows the direct extraction of parameters such as trigger voltage (Vt1), holding voltage (Vh), and on‐state resistance (Ron) through TLP testing, facilitating easy application to other types of DDSCR devices.

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Very small snapback silicon-controlled rectifier for electrostatic discharge protection in 28nm processing

Wang

Jin

Guo

et al. 2016

Microelectronics Reliability

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Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math> </inline-formula>/Metal Gate CMOS Process

Cited by 15 publications

References 10 publications

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Impacts of Floating Poly on Electrostatic Discharge Protection of Power-Managed High-Voltage Laterally Diffused Metal Oxide Semiconductor Components

Characteristic parameter model and circuit‐level simulation of gate‐controlled dual direction SCR for on‐chip ESD protection

Very small snapback silicon-controlled rectifier for electrostatic discharge protection in 28nm processing

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