Evidence for Lateral Angle Effect on Single-Event Latchup in 65 nm SRAMs

In harsh radiation environments, it is well known that the angle of incidence of impinging particles against the surface of the operating devices has significant effects on their sensitivity. This paper discusses the sensitivity underestimations that are made if particle isotropy is not taken into account, by means of an analytical study made with a single event upset predictive platform. To achieve this goal, experimental results carried out with a COTS bulk 130-nm non-volatile SRAM for various incident angles on 14.2 MeV neutrons are firstly discussed. Then, a modeling tool called MUSCA-SEP3 is used to predict the sensitivity of this memory under the same environmental conditions. Predictions and experimental results will be cross-checked, therefore the feasibility of this tool will be demonstrated for testing any other incident angle. Finally, an isotropic environment and an XY SRAM array will be emulated with MUSCA in order to demonstrate that the asymmetrical cross-sections that were observed experimentally for various incidence angles are due to the underlying asymmetry of the metalization/passivation layers within the device with respect to its active silicon. Conclusions will finally be drawn as for the importance of taking into account particle isotropy in radiationground tests.

Section: Introduction and Related Workmentioning

confidence: 99%

Experimental and Analytical Study of the Responses of Nanoscale Devices to Neutrons Impinging at Various Incident Angles

Korkian

Fabero

Hubert

et al. 2020

“…3(d). The large aspect ratio of sensitive volume could cause "lateral angle effect" of SEL sensitivity, which has been verified in reference [25]. It is under further study about SV number with latchup mechanism and memory array.…”

Section: B Sel Sensitivity Maps and Determination Of Sv Numbermentioning

confidence: 76%

“…Due to the close proximity, the SEL sensitive regions of adjacent memory cells within the same well could be combined together to be a single SEL sensitive region [18], [25]. So the SV number could be related to the well columns of the SRAM.…”

Section: B Sel Sensitivity Maps and Determination Of Sv Numbermentioning

confidence: 99%

Correction of Single Event Latchup Rate Prediction Using Pulsed Laser Mapping Test

Han

Feng

et al. 2015

Most classical approaches of single event effect rate prediction are based on the rectangular parallelepiped model of sensitive volume. However it is not clear about the number of sensitive volume in the device when predicting the in-flight single event latchup rate. As for memory device, there are two empirical practices to deal with the latchup sensitive volume number: one assumes that there is only one sensitive volume in the whole device; another assumes that there are as much sensitive volumes as the number of memory cells. The latchup sensitive volume number of a 4M-bits SRAM is determined as 63360 using pulsed laser mapping test in this work first. Based on the two assumed and measured sensitive volume number, the single event latchup rates of the device are calculated and compared. The results show that pulsed laser could be a powerful tool to obtain the real sensitive volume number in the device, which is significant for single event latchup rate prediction. The latchup rate will be either overestimated or underestimated with the assumption of the sensitive volume number as one or as much as the number of memory cells.Index Terms-In-flight rate, pulsed laser, sensitivity mapping, single event latchup (SEL), SRAM.

“…Furthermore, the effective LET metric is valid in this case because the angled irradiations were performed such that the ions traversed the long dimension of the SEL sensitive regions (i.e., parallel to the long N-and P-well stripes). This is also the worst-case ion trajectory for SEL [8], [9].…”

Section: Evidence Of the Effect Of Well Contact Densitiesmentioning

confidence: 99%

“…Moreover, Fig. 2 shows that the 45-nm SRAMs are more robust against SEL than the architecturally similar 65-nm SRAMs for which SEL data are given in [8]. The intrinsic process-level latchup robustness of the 45-nm technology makes latchup immunity an achievable goal through the use of hardening strategies.…”

Section: A Use Of External Resistors To Define Contact Density Requimentioning

confidence: 99%

Selection of Well Contact Densities for Latchup-Immune Minimal-Area ICs

Dodds

Hutson

Pellish

et al. 2010

Self Cite

Heavy ion data for custom SRAMs fabricated in a 45-nm CMOS technology demonstrate the effects of N-and P-well contact densities on single-event latchup. Although scaling has improved latchup robustness, process-level immunity has not been achieved, indicating a continued need for latchup mitigation techniques. A simple, algorithmic approach for selecting N-and P-well contact densities is described that ensures latchup immunity while minimizing the area penalty.Index Terms-Design rule, external resistor, hardening by design, latchup test structure, single-event latchup.