Investigation of External Latchup Robustness of Dual and Triple Well Designs in 65nm Bulk CMOS Technology

Abstract

In this work, the effect of design parameters on the internal and external latchup robustness of dual well (DW) and triple well (TW) test structures designed in 65nm bulk CMOS technology is studied. It is found that while both DW and TW latchup structures were robust for a positive-mode external latchup (latchup trigger current, ITRIG > 200mA), TW latchup structures were more susceptible to negative mode external latchup. The ITRIG for the worst case TW latchup structure was -50% lower compared to a similarly designed test structure in DW. Isolation of injection sources is more efficient in TW as compared to DW design and can be further improved by appropriate design of I/0 devices and guard rings surrounding the I/Os.

A new compact model for external latchup

“…Therefore, detectors with NBL's are expected to be more susceptible to external latchup. This conjecture is consistent with the measurement data in [15].…”

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Design techniques for low-voltage analog integrated circuits

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