Large‐tolerant “OptoBump” interface for interchip optical interconnections

Abstract

SUMMARYOptical interconnection technology for optical interboard and interchip connections will be an important technology in the next-generation communication equipment seeking a high-capacity throughput at the terabit per second level. With the objective of establishing an economical optical packaging technology, we propose an "optical I/O chip package," which is an optical package for the hybrid integration of optoelectric (O/E) devices and LSI chips that can be mounted on a printed-circuit board by standard surface mount technology (SMT). In this paper, we propose the OptoBump interface as the optical interconnection between the optical package and the board that connects these two elements by forming the microlens on both and using collimated light. Accommodating the fibers on the board and connecting the connectors become unnecessary because the connections having large beam diameters are able to tolerate offsets in the SMT mounting position. First, we calculated the required collimated beam diameter of 104 µm under the assumption of an SMT accuracy of ±50 µm.Next, we applied ray tracing to estimate the optical losses of the 45° mirror at the polymer optical waveguide facet integrated into the printed-circuit substrate and clearly exhibited the incident beam conditions with both improved losses and tolerances. And we integrated the polymer microlens into the polymer optical waveguide and the surface-emitting laser (VCSEL) and experimentally evaluated the optical coupling performance between them. The results verified a 1-dB tolerance at ±50 µm and demonstrated the effectiveness of this proposal.

Chip-level waveguide-mirror-pillar optical interconnect structure

“…Thus, a 45 angle is the intuitive choice for a mirror to couple light out of a waveguide at 90 . Example 45 mirror-terminated waveguide work for chip-substrate I/O interconnection include [2], [4], and [5]. In [2] and [4], the mirror is formed by dicing, while in [5], the mirror is direct laser-written.…”

“…For this to occur, schemes for out-of-plane coupling between a substrate and a chip that are compatible with conventional electrical I/O interconnects must be examined. One example scheme bonds active device arrays and a microprocessor onto an interposer that is, in turn, bonded onto a board with mirror-terminated waveguides [2]. A second scheme bonds dissimilar-material chips on a substrate with volume-grating couplers and compliant interconnects [3].…”

“…These are quasi-freespace solutions since the light propagating between the substrate and chip is not spatially confined. This necessitates using large lenses (230-m diameter [2]) and couplers (500-m length [3]) to account for 1) alignment tolerances due to assembly and 2) the coefficient of thermal expansion mismatch between the package-substrate and chip. In an attempt to address these compatibility and packaging constraints, polymer pillar chip I/O interconnects were introduced [6], [7].…”

Probe Module for Wafer-Level Testing of Gigascale Chips With Electrical and Optical I/O Interconnects

“…Although a simple structure, numerous variations of TWIs have been previously proposed for use as electrical [34][35][36][37], optical [38,39], and microfluidic [40][41][42] conduits. The novelty of this work is the realization of high-density electrical TWIs as well as guided-wave optical TWIs (Chapter IV).…”

Polymer Pillars as Optical I/O for Gigascale Chips using Mirror-Terminated Waveguides

“…An example includes bonding detector and VCSEL arrays onto a microprocessor that is attached to an interposer, which is bonded to a board with mirrorterminated waveguides [5]. Another example is the attachment of different chips on a single board using compliant interconnects and volume-grating couplers [6].…”