Key impediments to dft-focused test and how to overcome them

Posse, K.; Eide, Geir Egil

doi:10.1109/test.2003.1270876

Cited by 5 publications

(4 citation statements)

References 7 publications

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“…Moreover, because when no the synchronization overhead is induced the VTD in bits equals the TAT in ATE clock cycles, the reduction in VTD equals the reduction in TAT. Furthermore, at-speed structural test can be facilitated by using on-chip test controllers without some of the drawbacks of the slowfast clock approach [23], as illustrated next.…”

Section: Resultsmentioning

confidence: 99%

“…In addition, since the on-chip test controller ensures clock generation at on-chip frequencies, the proposed distribution architecture represents a Load Slow/Run Fast environment which is very suitable for DFT-focused test [23]. Thus, we can achieve at-speed structural test without some of the drawbacks of using a typical slow-fast clock approach, such as using programmable PLLs for generating the launch and capture clocking [23]. It should also be noted that the TAP controller will require to only shift data, the update and capture states are not used for internal test with the proposed architecture.…”

Section: Implementation Issuesmentioning

confidence: 99%

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Synchronization overhead in SOC compressed test

Gonciari

Al-Hashimi

Nicolici

2005

IEEE Trans. VLSI Syst.

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Abstract-Test data compression is an enabling technology for low-cost test. Compression schemes however, require communication between the system under test and the automated test equipment. This communication, referred to in this paper as synchronization overhead, may hinder the effective deployment of this new test technology for core-based systems-on-a-chip. This paper analyzes the sources of synchronization overhead and discusses the different trade-offs, such as area overhead, test time and automatic test equipment extensions. A novel scalable and programmable on-chip distribution architecture is proposed, which addresses the synchronization overhead problem and facilitates the use of low cost testers for manufacturing test. The design of the proposed architecture is introduced in a generic framework, and the implementation issues (including the test controller and test set preparation) have been considered for a particular case.

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Section: Resultsmentioning

confidence: 99%

Section: Implementation Issuesmentioning

confidence: 99%

Synchronization overhead in SOC compressed test

Gonciari

Al-Hashimi

Nicolici

2005

IEEE Trans. VLSI Syst.

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“…Through pattern-editing experiments, four (4) candidates were chosen. This was done using a tabletop DFT (design for test)-focused tester, where the input patterns could be created from scratch and the resulting pass/fail outputs could be interpreted for chain behavior [7]. With the DUT die's backside exposed, the part could then be inspected using Electro Optical Probing.…”

Section: Figure 5: the Highlight On The 2 Nd "L" Indicates A Failed Test Meaning The Data Detected Is A "H"mentioning

confidence: 99%

Electro-Optical Probing for Capturing Fast-to-Rise Scan Chain Failures

Villareal

Estores

Baert

2021

International Symposium for Testing and Failure Analysis

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The paper discusses an imaging sensor exhibiting a fast-to-rise sanity check failure from a scan chain test. The DUT was prepared for backside analysis in a portable daughter-card [1] that enabled the analyst to easily shift between testing platforms such as a standard imaging tester bench and compact scan diagnosis system [2], while being inspected under the Electro-Optical Probing (EOP) machine. To find a failing flip-flop in several-thousands long chain, broken scan chain analysis was performed to narrow down the search to a few chain links was implemented. EOP methods of fault isolation were employed to verify the location of the broken scan cell in those selected flip-flops. Finally, parallel lapping was done to confirm the location of the failing flip-flop under a SEM.

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“…Recently, the test-processor-per-pin tester and the time driven tester have been developed [5]. Testers that focus on design for testability (DFT) have also been introduced to the market [6,7]. A board-mounted tester for a dedicated chip was also developed [8].…”

Section: Introductionmentioning

confidence: 99%

Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development

Sato¹,

Wakamatsu²,

Arai³

et al. 2008

Journal of Information Processing Systems

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VLSI chips have been tested using various automatic test equipment (ATE). Although each ATE has a similar structure, the language for ATE is proprietary and it is not easy to convert a test program for use among different ATE vendors. To address this difficulty we propose a tester structure expression language, a tester language with a novel format. The developed language is called the general tester language (GTL). Developing an interpreter for each tester, the GTL program can be directly applied to the ATE without conversion. It is also possible to select a cost-effective ATE from the test program, because the program expresses the required ATE resources, such as pin counts, measurement accuracy, and memory capacity. We describe the prototype environment for the GTL and the tester selection tool. The software size of the prototype is approximately 27,800 steps and 15 manmonths were required. Using the tester selection tool, the number of man-hours required in order to select an ATE could be reduced to 1/10. A GTL program was successfully executed on actual ATE.

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Key impediments to dft-focused test and how to overcome them

Cited by 5 publications

References 7 publications

Synchronization overhead in SOC compressed test

Synchronization overhead in SOC compressed test

Electro-Optical Probing for Capturing Fast-to-Rise Scan Chain Failures

Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development

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