Synchronization overhead in SOC compressed test

Gonciari, P.T.; Al-Hashimi, Bashir M.; Nicolici, Nicola

doi:10.1109/tvlsi.2004.834238

Cited by 28 publications

(5 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…If the ATE has handshaking capabilities, then the (inverted) output of the decoding logic can be used for notifying it to send the next seed. Otherwise, a small FIFO buffer can be used between the ATE and the LFSR [5].…”

Section: B Proposed Architecturementioning

confidence: 99%

LFSR-based test-data compression with self-stoppable seeds

Koutsoupia

Kalligeros

Kavousianos

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

Abstract-The main disadvantage of LFSR-based compression is that it should be usually combined with a constrained ATPG process, and, as a result, it cannot be effectively applied to IP cores of unknown structure. In this paper, a new LFSR-based compression approach that overcomes this problem is proposed. The proposed method allows each LFSR seed to encode as many slices as possible. For achieving this, a special purpose slice, called stop-slice, that indicates the end of a seed's usage is encoded as the last slice of each seed. Thus, the seeds include by construction the information of where they should stop and, for that reason, we call them self-stoppable. A stop-slice generation procedure is proposed that exploits the inherent test set characteristics and generates stop slices which impose minimum compression overhead. Moreover, the architecture for implementing the proposed technique requires negligible additional hardware overhead compared to the standard LFSR-based architecture. The proposed technique is also accompanied by a seed calculation algorithm that tries to minimize the number of calculated seeds.

show abstract

Section: B Proposed Architecturementioning

confidence: 99%

LFSR-based test-data compression with self-stoppable seeds

Koutsoupia

Kalligeros

Kavousianos

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…However, the general framework proposed in [19] can be applied to reduce the impact of synchronization overhead.…”

Section: B Fsm Designmentioning

confidence: 99%

Efficient test compression technique based on block merging

El-Maleh

2008

IET Comput. Digit. Tech.

View full text Add to dashboard Cite

Test data compression is an effective methodology for reducing test data volume and testing time. In this paper, we present a new test data compression technique based on block merging. The technique capitalizes on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes advantage of cases where the merged block can be filled by all 0's or all 1's. Test data decompression is performed on chip using a simple circuitry that repeats the merged block the required number of times. The decompression circuitry has the advantage of being test data independent. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique compared to other coding-based compression techniques.

show abstract

“…While these techniques can deliver the actual test vectors intact, the indeterminacy in the expansion ratio of the codewords imposes significant synchronization problems, for which [4] provides an in-depth INTERNATIONAL TEST CONFERENCE Paper 35.2 analysis along with a distributed architecture proposed to solve the problem in a scalable manner. Another test set dependent solution consists of a dictionary based compression approach [5].…”

Section: Previous Workmentioning

confidence: 99%

Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors

Sinanoglu

2008

2008 IEEE International Test Conference

View full text Add to dashboard Cite

While test stimulus compression helps reduce test time and data volume, and thus alleviates test costs, the delivery of certain test vectors may not be possible, leading to test quality degradation. Whether a test vector is encodable in the presence of a decompressor strongly hinges on the distribution ofits care bits. In this paper, we present a technique that provides an on-chip capability tojudiciously manipulate care bit distribution of a test vector We thus propose a hardware block, namely, Align-Encode, to be utilized along with any decompressor to boost the effectiveness ofthe decompressor. Align-Encode is reconfigured on a per pattern basis to delay the shift-in operations in selected scan chains, in order to align the scan slices in such a way that more test vectors become encodable. The reconfigurability ofAlign-Encode provides a test pattern independent solution, wherein any given set oftest vectors can be analyzed to compute the proper delay information. We map the delay computation problem to the maximal clique problem, and utilize an efficient heuristic to provide a near-optimal solution. Experimental results also justify the test pattern encodability enhancements that Align-Encode delivers, enabling significant test quality improvements andlor test cost reductions even when used with simple decompressors.

show abstract

Synchronization overhead in SOC compressed test

Cited by 28 publications

References 25 publications

LFSR-based test-data compression with self-stoppable seeds

LFSR-based test-data compression with self-stoppable seeds

Efficient test compression technique based on block merging

Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors

Contact Info

Product

Resources

About