Efficient test compression technique based on block merging

Abstract

Test data compression is an effective methodology for reducing test data volume and testing time. In this paper, we present a new test data compression technique based on block merging. The technique capitalizes on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes advantage of cases where the merged block can be filled by all 0's or all 1's. Test data decompression is performed on chip using a simple circuitry that repeats the merged block the required number of times. The decompression circuitry has the advantage of being test data independent. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique compared to other coding-based compression techniques.

A Multi-dimensional Pattern Run-Length Method for Test Data Compression

“…As shown, the proposed methods are all very efficient in computation. Finally, with the above conclusions, we compare The proposed 2.5D-PRC with other coding-based run-length compression methods such as GOLOMB [11], FDR [12], ALT-FDR [13], EFDR [15], Huffman-coding-based SHC [7], VIHC [9], RL-HC [17], 9C [10] and BM [16]. The comparison results are presented in Table III, as can be seen, the proposed MD-PRC outperforms other methods in most cases.…”

“…The compression is data-independent and the program for decompression is very small and simple, thereby allowing fast and high throughput to minimize test time. Recently, BM [16], a block merging technique, was proposed by El-Maleh in which good compression effect was achieved by encoding runs of fixed-length blocks, only the merged block and number of block merged are recorded. The RL-HC [17] combines the above two well-known methods: run-length-based and Huffman coding for scan testing to reduce test data volume, test application time, and scan-in power.…”

A Power Efficient Test Data Compression Method on Count Compatible PRL Coding

“…The decoder command is less and suitable for on-chip implementation. Recently, block merging (BM) 15 is proposed by El-Maleh in which good compression e®ect is achieved by coding runs of¯xed-length blocks, only the merged block and number of block merged are recorded. The mixed run-length and Hu®man coding (RL-HC) 16 is proposed for scan testing to reduce test data volume, test application time and scanned-in power.…”

Test data compression using alternating variable run-length code

“…Test data volume and power reduction can be achieved by utilizing a built-in self-test (BIST) [5][6][7], test compaction [8,9] and test compression techniques [3,4,[10][11][12][13][14][15][16][17][18][19][20][21][22]. However, BIST requires a longer test application time, and it is extensively used for memory testing but is not common for logic testing [17].…”